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using mpmc ddr2 controller with an other processor

Started by rpon...@gmail.com March 24, 2008
hi groups !

what is the best route in order to use an edk generated mpmc ddr2
controller with a custom processor (not microblaze, but gaisler leon3
or even picoblaze ; this is for edu. purpose...) ?

I have a copy the ddr2_sdram_wrapper.ngc and
clock_generator_0_wrapper.ngc files (these are good, tested with a
microblaze design).

I read xilinx mpmc.pdf but I am lost ... I think I need interface my
cpu with opbv46 port 0, that is :
      SPLB0_Clk : in std_logic;
      SPLB0_Rst : in std_logic;
      SPLB0_PLB_ABus : in std_logic_vector(0 to 31);
      SPLB0_PLB_PAValid : in std_logic;
      SPLB0_PLB_SAValid : in std_logic;
      SPLB0_PLB_masterID : in std_logic_vector(0 to 0);
      SPLB0_PLB_RNW : in std_logic;
      SPLB0_PLB_BE : ...

is there a reference design somewhere...?

I know I should use mig, but this seems not be an easy task too...

best regards,
raph
On Mar 24, 9:18 am, "rpons...@gmail.com" <rpons...@gmail.com> wrote:
> hi groups ! > > what is the best route in order to use an edk generated mpmc ddr2 > controller with a custom processor (not microblaze, but gaisler leon3 > or even picoblaze ; this is for edu. purpose...) ? > > I have a copy the ddr2_sdram_wrapper.ngc and > clock_generator_0_wrapper.ngc files (these are good, tested with a > microblaze design). > > I read xilinx mpmc.pdf but I am lost ... I think I need interface my > cpu with opbv46 port 0, that is : > SPLB0_Clk : in std_logic; > SPLB0_Rst : in std_logic; > SPLB0_PLB_ABus : in std_logic_vector(0 to 31); > SPLB0_PLB_PAValid : in std_logic; > SPLB0_PLB_SAValid : in std_logic; > SPLB0_PLB_masterID : in std_logic_vector(0 to 0); > SPLB0_PLB_RNW : in std_logic; > SPLB0_PLB_BE : ... > > is there a reference design somewhere...? > > I know I should use mig, but this seems not be an easy task too... > > best regards, > raph
If you want to interface the MPMC (any version from 2.x up to the 3.x found in EDK 9.2), you're best bet is to look at the NPI (Native Port Interface). That's what every port on the MPMC interfaces to. The MPMC uses it as the base interface, and then when you instantiate a OPB, PLB, XCL, etc port it has a wrapper that sits on top of the NPI. The NPI provides a simple direct-to-the-FIFO interface of the MPMC. Be careful following the documented standard, though. It is very picky and sometimes some of the 'protocol' is not 100% documented and is inferred. This will allow you to create your own wrapper to connect to any other bus.