Dear all <BR> I am using Xilinx Foundation 3.1i to implement my <BR> design into XSV board and debug using hardware <BR> debugger. <BR> I am trying to instantiate readback symbol in my <BR> design using this file : <p> library IEEE; <BR> use IEEE.std_logic_1164.all; <BR> library virtex; <BR> use virtex.components.all; <p> entity rdbk is <BR> port ( <BR> rt, clk : in STD_LOGIC; <BR> rd, rip_p : out STD_LOGIC <BR> ); <BR> end rdbk; <p> architecture xilinx of rdbk is <p> begin <p> U0: RDBK port map (TRIG => rt, DATA => rd, RIP => <BR> rip_p); <BR> U1: RDCLK port map (I => clk); <p> end xilinx; <p> But I found these errors at implementation steps : <p> Error L-3/C0 : #0 Error: <BR> :/Xilinx/active/projects/and3_gat/readback.vhd line <BR> -3 Library logical name VIRTEX is not mapped to a <BR> host directory. (VSS-1071) (FPGA-hci-hdlc-unknown) <BR> Error L4/C0 : #0 Error: <BR> E:/Xilinx/active/projects/and3_gat/readback.vhd line <BR> 4 No selected element named COMPONENTS is defined <BR> for this prefix. (VSS-573) <BR> Error L13/C0 : #0 Error: <BR> E:/Xilinx/active/projects/and3_gat/readback.vhd line <BR> 13 The intermediate file for entity RDBK is not in <BR> the library bound to WORK. (VSS-1084) <p> What do they mean ? I really apreciate the feedback <BR> from all of you. <p> Regards <p> Nyoman Yani
Virtex: Foundation 3.1 Error
Started by ●August 13, 2003