Modify POF with new ESB (ROM) content?

Antti wrote:
<snip>
> 
> quit simple
> 
> if you want to deliver a BITFILE only and allow the client to
> change the software but not the FPGA bit file itself.
> 
> this is VERY simple with Xilinx tools
> and IMPOSSIBLE with Altera tools

Sounds like simple common sense - what is it that prevents
Altera from offering this ? - and why did they miss
this obvious flow ?

-jg

Antti <Antti.Lukats@googlemail.com> writes:

> good god... how can it be that you dont understand...

I do understand the difference between the two. I've used both tools.

> the ELF to BIT merge is much simpler than the cdb_mif update

I know that it's simpler. But when you have the RTL source there is no
practical difference. At least it's not for me. It only takes a couple
seconds to run the merge in each case.

But if you have lost the source (like the OP) or will not give some
3rd party the Quartus project file then quartus_cdb will not help you.

Petter
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On Apr 8, 5:33 pm, Petter Gustad <newsmailco...@gustad.com> wrote:

> I know that it's simpler. But when you have the RTL source there is no
> practical difference. At least it's not for me. It only takes a couple
> seconds to run the merge in each case.
>
> But if you have lost the source (like the OP) or will not give some
> 3rd party the Quartus project file then quartus_cdb will not help you.

*If* you have RTL source, and *if* you have it in the right place.

I've tried to explain this to Altera reps several times, and they just
don't get it that their
tool is much less capable than Xilinx's in this area.  It's
effectively like saying that you
have to have design documents for your entire PC on hand if you want
to install
an updated BIOS...

There are some hints out there that it may not be too hard to reverse
engineer

Jim Granville <no.spam@designtools.maps.co.nz> wrote:
> Antti wrote:
> <snip>
> > 
> > quit simple
> > 
> > if you want to deliver a BITFILE only and allow the client to
> > change the software but not the FPGA bit file itself.
> > 
> > this is VERY simple with Xilinx tools
> > and IMPOSSIBLE with Altera tools

> Sounds like simple common sense - what is it that prevents
> Altera from offering this ? - and why did they miss
> this obvious flow ?

B.t.w two questions:
- can anybody give an example commandline for a real world DATA2MEM
  example?
- can any FPGA family BRAM be written by JTAG directly without
  upsetting the rest of the FPGA configuration?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On 2008-04-08, Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
> B.t.w two questions:
> - can anybody give an example commandline for a real world DATA2MEM
>   example?

I have one example of this in my PPC405 design at
http://www.da.isy.liu.se/~ehliar/stuff/ppc405-mini-v1.0.tar.gz

(No EDK required to test it.)

/Andreas

On Tue, 8 Apr 2008 06:01:33 -0700 (PDT), Antti <Antti.Lukats@googlemail.com>
wrote:

>On 8 Apr., 14:59, Petter Gustad <newsmailco...@gustad.com> wrote:
>> Antti <Antti.Luk...@googlemail.com> writes:
>> > On 8 Apr., 13:22, Petter Gustad <newsmailco...@gustad.com> wrote:
>> >> Antti <Antti.Luk...@googlemail.com> writes:
>> >> > a DATA2MEM (elf to bit file merge) is VERY important for softcore
>> >> > processors in FPGA's, and Altera kinda claims they have NIOS and
>> >> > stuff, but the MOST IMPORTANT too for FPGA-soc is missing from their
>> >> > toolchain!!
>>
>> >> You can get the same functionality using
>>
>> >> quartus_cdb --update_mif
>> > to my knowledge YOU CAN NOT
>>
>> > if Quartus has generated a bit file (programming file)
>> > then this file (without access to the project database)  CAN NOT BE
>> > updated with new memory file, unlike it is possible with xilinx
>> > data2mem tool
>>
>> If you have lost track of the source/project database (like the OP)
>> you can not. But for the functional purpose where you run make on you
>> NIOS software project and merge the generated mif/hex file into a new
>> sof file without recompiling the project you can.
>the all IDEA about the update is that you need 2 files
>
>1) BIT file
>2) ELF file
>
>and nothing else.. if based on those 2 files the elf can not be
>merged, then this is REALLY BAD!!!

Well, I thought I needed the .bmm file too, any time I've tried it. 
How do you map addresses and data slices into specific BRAMs otherwise?

So 3 files, one of which comes from the original project. 
But it's just a straightforward text file.

- Brian

Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> writes:

> B.t.w two questions:
> - can anybody give an example commandline for a real world DATA2MEM
>   example?

It's been a while (don't have access to ISE at the moment), but
I've usually done this through bitinit, something like:

bitinit system.mhs  -bm system.bmm -pe ppc405_0 executable.elf -bt old.bit -o new.bit

Somebody else probably have a similar data2mem command laying around somewhere.

> - can any FPGA family BRAM be written by JTAG directly without
>   upsetting the rest of the FPGA configuration?

That's what I normally do with the NIOS software. It depends on how
your application will handle that your software is replaced with a new
version on-the-fly.

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
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Q: What is the most annoying thing on usenet and in e-mail?