OBUF gate delay

Started by April 8, 2008
Hi,
   I am using virtex4 device for my designs. In timing analysis i
found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is
that a way , i can reduce this gate delay by giving some constraints.
ie  is to reduce the gate delay  by tools .


<jamicrotech@gmail.com> wrote in message 
news:3234335a-7821-41f1-b69d-fa6dcad78e68@q1g2000prf.googlegroups.com...
> Hi, > I am using virtex4 device for my designs. In timing analysis i > found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is > that a way , i can reduce this gate delay by giving some constraints. > ie is to reduce the gate delay by tools . > >
In your .ucf file try something like this:- NET "I_CANT_BE_BOTHERED_TO_RTFM" SLEW=FAST; Or, better still, read the constraints guide. HTH., Syms.
jamicrotech@gmail.com wrote:
> Hi, > I am using virtex4 device for my designs. In timing analysis i > found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is > that a way , i can reduce this gate delay by giving some constraints. > ie is to reduce the gate delay by tools .
Are your outputs synchronous with the output registers in the IOB? That's step 1. It sounds like you may have the FAST attribute turned on through I'm not as familiar with the V4 as the Spartan families. Double-check your pin report (pad report?) to verify your output has the I/O standard and FAST attribute you request. The next thing most designers consider is a DCM generated clock to effectively reduce the clock-to-out time. Getting onto the chip has delays. Getting off the chip has delays. There's no getting around the delays *but* you can compensate for some of this with the DCM. If your system clock is regular and reasonably jitter free, this is a superb way to go. If your system clock is irregular or subject to strong jitter hits, the DCM won't help but it's usable in most board designs. I'd suggest you dig far enough into any part datasheet before starting a design with the part to understand what the I/O timing should be to put together a system-level timing budget. If you have 5 ns periods with 4 ns clock-to out and 3 ns setup times, you may be starting with a non-solution. Since you already have your design, read up on how to use the DCMs and verify that the OBUF timing corresponds to what you would expect from the I/O numbers in the data sheet for that speed grade. If your outputs aren't registered with I/O registers, look into whether you can do that without otherwise crippling the design; it's the first tool to get good I/O numbers. - John_H
"Symon" <symon_brewer@hotmail.com> wrote in message 
news:ftfp5l$4go$1@aioe.org...
> > <jamicrotech@gmail.com> wrote in message > news:3234335a-7821-41f1-b69d-fa6dcad78e68@q1g2000prf.googlegroups.com... >> Hi, >> I am using virtex4 device for my designs. In timing analysis i >> found OBUF in V4 is 3.79ns which is a big obstacle for my design . Is >> that a way , i can reduce this gate delay by giving some constraints. >> ie is to reduce the gate delay by tools . >> >> > > In your .ucf file try something like this:- > > NET "I_CANT_BE_BOTHERED_TO_RTFM" SLEW=FAST; > > Or, better still, read the constraints guide. > > HTH., Syms. > >
...oh, and changing the drive strength will also affect the output delay. This can also be set by a UCF constraint. You've read DS302, right? HTH., Syms.