Which to learn: Verilog vs. VHDL?

Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
Kit with Xilinx ISE. I am an electrical engineer by training and did
some verilog in my collegiate days - but that was quite some time ago
and it is all very fuzzy now. I have decided that as an EE I should be
familiar with FPGAs - so I'm re-educating myself. With that said -
which would be more useful to learn in the industrial world: Verilog
or VHDL?

Thanks!

-Michael

Michael wrote:
> which would be more useful to learn in the industrial world: Verilog
> or VHDL?

Better learn both.
This has been well covered:
http://groups.google.com/groups/search?q=vhdl+vs+verilog

      -- Mike Treseler

>which would be more useful to learn in the industrial world: Verilog
>or VHDL?

In Europe (including UK) VHDL is more commonly used.

In USA Verilog is prevalent.

However, SystemVerilog is gradually gaining ground everywhere, and
Verilog-2001 is a subset of SV.

It is probably very difficult to learn both simultaneously...

Michael wrote:
> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
> Kit with Xilinx ISE. I am an electrical engineer by training and did
> some verilog in my collegiate days - but that was quite some time ago
> and it is all very fuzzy now. I have decided that as an EE I should be
> familiar with FPGAs - so I'm re-educating myself. With that said -
> which would be more useful to learn in the industrial world: Verilog
> or VHDL?
> 
> Thanks!
> 
> -Michael
Verilog is better, but VHDL is used more in FPGAs.  SystemVerilog (a 
Verilog superset) is the future, but in the FPGA world, the future is 
often further away than you'd think.  (Verilog-2001 features are still 
lacking in some tools.)  The far future is sequential C-to-gates.  Teach 
that to your grandchildren.  -Kevin

Michael wrote:
> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
> Kit with Xilinx ISE. I am an electrical engineer by training and did
> some verilog in my collegiate days - but that was quite some time ago
> and it is all very fuzzy now. I have decided that as an EE I should be
> familiar with FPGAs - so I'm re-educating myself. With that said -
> which would be more useful to learn in the industrial world: Verilog
> or VHDL?
> 
> Thanks!
> 
> -Michael

I personally found verilog very intuitive with my software engineering 
background. VHDL on the other hand seems weird to me. YMMY.

Fei

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message 
news:fu2k7i$aep1@cnn.xsj.xilinx.com...
> Michael wrote:
>> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
>> Kit with Xilinx ISE. I am an electrical engineer by training and did
>> some verilog in my collegiate days - but that was quite some time ago
>> and it is all very fuzzy now. I have decided that as an EE I should be
>> familiar with FPGAs - so I'm re-educating myself. With that said -
>> which would be more useful to learn in the industrial world: Verilog
>> or VHDL?
>>
>> Thanks!
>>
>> -Michael
> Verilog is better, but VHDL is used more in FPGAs.

Statements like this are best described with the help of a bit of 
multimedia:

http://www.youtube.com/watch?v=0PSMr_0qCak

Hans
www.ht-lab.com


> SystemVerilog (a Verilog superset) is the future, but in the FPGA world, 
> the future is often further away than you'd think.  (Verilog-2001 features 
> are still lacking in some tools.)  The far future is sequential 
> C-to-gates.  Teach that to your grandchildren.  -Kevin 

On Apr 14, 9:18 am, Michael <nleah...@gmail.com> wrote:
> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
> Kit with Xilinx ISE. I am an electrical engineer by training and did
> some verilog in my collegiate days - but that was quite some time ago
> and it is all very fuzzy now. I have decided that as an EE I should be
> familiar with FPGAs - so I'm re-educating myself. With that said -
> which would be more useful to learn in the industrial world: Verilog
> or VHDL?
>
> Thanks!
>
> -Michael

The syntax for Verilog will be a bit more familiar to you if you
program in C/C++.  Don't let this keep you from seeing it as
synthesizable hardware though.  It takes practice to keep from coding
garbage that is unsynthesizable.
Verilog is also a bit easier with syntax and requires somewhat fewer
lines to do the same thing.

Also if you know one, the other is pretty easy to read.  A book I used
as a reference in my Digital ASIC class has great examples of both:

Hdl Chip Design: A Practical Guide for Designing, Synthesizing &
Simulating Asics & Fpgas Using Vhdl or Verilog by Douglas J. Smith

I bought it for $65, amazon has a ridiculous price of $284, WTF? don't
get it from them.

That said, it is not like C vs Python where the entire philosophy is
different.  And it is hard to read one vs. the other

Kevin Neilson wrote:
> Verilog is better,
  ^^^^^^^^^^^^^^^^^

That's far too broad a generalization.  Verilog might have some advantages,
but it's not clearly *better*.

> but VHDL is used more in FPGAs.

I'm not sure whether that's actually true overall, though it seems to be
true in some geographic areas.

lm317t wrote:
> The syntax for Verilog will be a bit more familiar to you if you
> program in C/C++.

Which is a drawback, not a benefit, since the actual langauge semantics
are almost nothing like C.  The superficial similarity of the syntax
seems to cause a lot of confusion for new Verilog designers.

On Apr 15, 9:01 pm, Eric Smith <e...@brouhaha.com> wrote:
> lm317t wrote:
> > The syntax for Verilog will be a bit more familiar to you if you
> > program in C/C++.
>
> Which is a drawback, not a benefit, since the actual langauge semantics
> are almost nothing like C.  The superficial similarity of the syntax
> seems to cause a lot of confusion for new Verilog designers.

I'm just stating my anecdotal experience, but for me the syntax
similarity helped me by not forcing me to learn new syntax.  How does
this cause confusion?  I think the biggest source of confusion for new
HDL designers in general is thinking in parallel hardware, not
sequential instructions like with a programming language.  This is
true regardless of HDL.  I can't say I've heard of the C syntax
causing confusion with C vs. VHDL.  Anyone else here have any relevant
experience or evidence for this?