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Snythesis error

Started by Thorsten Kiefer ●April 15, 2008
Hi,
when I synthesize the following, I get warnings.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity debounce is
        generic(N : integer := 20);
        port(
                clk,reset : in std_logic;
                button : in std_logic;
                debounced : out std_logic
        );
end debounce;

architecture Behavioral of debounce is
        type state_type is (s0,s1);
        signal state_reg,state_next : state_type;
        signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
begin
        process(clk,reset)
        begin
                if reset='1' then
                        state_reg <= s0;
                        cnt_reg <= (others => '0');
                elsif clk'event and clk='1' then
                        state_reg <= state_next;
                        cnt_reg <= cnt_next;
                end if;
        end process;

        process(state_reg,cnt_reg,button)
        begin
                if state_reg=s0 and cnt_reg=2**N-1 then
                        state_next <= s1;
                        cnt_next <= (others=>'0');
                elsif state_reg=s0 and button='0' then
                        state_next <= s0;
                        cnt_next <= (others=>'0');
                elsif state_reg=s0 and button='1' then
                        state_next <= s0;
                        cnt_next <= cnt_next + 1;
                elsif state_reg=s1 and cnt_reg=2**N-1 then
                        state_next <= s0;
                        cnt_next <= (others=>'0');
                elsif state_reg=s1 and button='1' then
                        state_next <= s1;
                        cnt_next <= (others=>'0');
                elsif state_reg=s1 and button='0' then
                        state_next <= s1;
                        cnt_next <= cnt_next + 1;
                else
                        state_next <= state_reg;
                        cnt_next <= cnt_reg;
                end if;
        end process;
        
        debounced <= '0' when state_reg=s0 else '1';
end Behavioral;


Warnings : 
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.


What does this mean ?

Best Regards
Thorsten
Reply by John_H ●April 15, 20082008-04-15
Thorsten Kiefer wrote:

> Hi,
> when I synthesize the following, I get warnings.
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use ieee.numeric_std.all;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity debounce is
>         generic(N : integer := 20);
>         port(
>                 clk,reset : in std_logic;
>                 button : in std_logic;
>                 debounced : out std_logic
>         );
> end debounce;
>
> architecture Behavioral of debounce is
>         type state_type is (s0,s1);
>         signal state_reg,state_next : state_type;
>         signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
> begin
>         process(clk,reset)
>         begin
>                 if reset='1' then
>                         state_reg <= s0;
>                         cnt_reg <= (others => '0');
>                 elsif clk'event and clk='1' then
>                         state_reg <= state_next;
>                         cnt_reg <= cnt_next;
>                 end if;
>         end process;
>
>         process(state_reg,cnt_reg,button)
>         begin
>                 if state_reg=s0 and cnt_reg=2**N-1 then
>                         state_next <= s1;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='0' then
>                         state_next <= s0;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='1' then
>                         state_next <= s0;
>                         cnt_next <= cnt_next + 1;
>                 elsif state_reg=s1 and cnt_reg=2**N-1 then
>                         state_next <= s0;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s1 and button='1' then
>                         state_next <= s1;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s1 and button='0' then
>                         state_next <= s1;
>                         cnt_next <= cnt_next + 1;
>                 else
>                         state_next <= state_reg;
>                         cnt_next <= cnt_reg;
>                 end if;
>         end process;
>
>         debounced <= '0' when state_reg=s0 else '1';
> end Behavioral;
>
>
> Warnings :
> =========================================================================
> *                         Low Level Synthesis                           *
> =========================================================================
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.
>
>
> What does this mean ?
>
> Best Regards
> Thorsten


You have two instances of cnt_next <= cnt_next + 1 where you probably
want cnt_next <= cnt_reg + 1.

Happy coding!
Reply by Thorsten Kiefer ●April 15, 20082008-04-15
John_H wrote:


> Thorsten Kiefer wrote:
>> Hi,
>> when I synthesize the following, I get warnings.
>>
>> library IEEE;
>> use IEEE.STD_LOGIC_1164.ALL;
>> use ieee.numeric_std.all;
>>
>> ---- Uncomment the following library declaration if instantiating
>> ---- any Xilinx primitives in this code.
>> --library UNISIM;
>> --use UNISIM.VComponents.all;
>>
>> entity debounce is
>>         generic(N : integer := 20);
>>         port(
>>                 clk,reset : in std_logic;
>>                 button : in std_logic;
>>                 debounced : out std_logic
>>         );
>> end debounce;
>>
>> architecture Behavioral of debounce is
>>         type state_type is (s0,s1);
>>         signal state_reg,state_next : state_type;
>>         signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
>> begin
>>         process(clk,reset)
>>         begin
>>                 if reset='1' then
>>                         state_reg <= s0;
>>                         cnt_reg <= (others => '0');
>>                 elsif clk'event and clk='1' then
>>                         state_reg <= state_next;
>>                         cnt_reg <= cnt_next;
>>                 end if;
>>         end process;
>>
>>         process(state_reg,cnt_reg,button)
>>         begin
>>                 if state_reg=s0 and cnt_reg=2**N-1 then
>>                         state_next <= s1;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='0' then
>>                         state_next <= s0;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='1' then
>>                         state_next <= s0;
>>                         cnt_next <= cnt_next + 1;
>>                 elsif state_reg=s1 and cnt_reg=2**N-1 then
>>                         state_next <= s0;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s1 and button='1' then
>>                         state_next <= s1;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s1 and button='0' then
>>                         state_next <= s1;
>>                         cnt_next <= cnt_next + 1;
>>                 else
>>                         state_next <= state_reg;
>>                         cnt_next <= cnt_reg;
>>                 end if;
>>         end process;
>>
>>         debounced <= '0' when state_reg=s0 else '1';
>> end Behavioral;
>>
>>
>> Warnings :
>> =========================================================================
>> *                         Low Level Synthesis                           *
>> =========================================================================
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.
>>
>>
>> What does this mean ?
>>
>> Best Regards
>> Thorsten
> 
> You have two instances of cnt_next <= cnt_next + 1 where you probably
> want cnt_next <= cnt_reg + 1.
> 
> Happy coding!


THX !!
Reply by Kevin Neilson ●April 15, 20082008-04-15
>         process(state_reg,cnt_reg,button)
>         begin
>                 if state_reg=s0 and cnt_reg=2**N-1 then
>                         state_next <= s1;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='0' then
>                         state_next <= s0;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='1' then
>                         state_next <= s0;
>                         cnt_next <= cnt_next + 1;



> 

I think the line above shows how the combinatorial loop is formed, 
because you're making a value in a combinatorial process a function of 
itself.  I think what you really want is:

 >                         cnt_next <= cnt_reg + 1;

I recommend putting the whole state machine in a single clocked process. 
  It makes the state machine easier to maintain and then you avoid 
having two names for registers and you avoid having combinatorial loops. 
  One side effect is that actions happen not in the named state but 
during the next state.
-Kevin
Reply by Andy Peters ●April 15, 20082008-04-15
On Apr 15, 8:18 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:

> Hi,
> when I synthesize the following, I get warnings.
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use ieee.numeric_std.all;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity debounce is
>         generic(N : integer := 20);
>         port(
>                 clk,reset : in std_logic;
>                 button : in std_logic;
>                 debounced : out std_logic
>         );
> end debounce;
>
> architecture Behavioral of debounce is
>         type state_type is (s0,s1);
>         signal state_reg,state_next : state_type;
>         signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
> begin
>         process(clk,reset)
>         begin
>                 if reset='1' then
>                         state_reg <= s0;
>                         cnt_reg <= (others => '0');
>                 elsif clk'event and clk='1' then
>                         state_reg <= state_next;
>                         cnt_reg <= cnt_next;
>                 end if;
>         end process;
>
>         process(state_reg,cnt_reg,button)
>         begin
>                 if state_reg=s0 and cnt_reg=2**N-1 then
>                         state_next <= s1;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='0' then
>                         state_next <= s0;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s0 and button='1' then
>                         state_next <= s0;
>                         cnt_next <= cnt_next + 1;
>                 elsif state_reg=s1 and cnt_reg=2**N-1 then
>                         state_next <= s0;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s1 and button='1' then
>                         state_next <= s1;
>                         cnt_next <= (others=>'0');
>                 elsif state_reg=s1 and button='0' then
>                         state_next <= s1;
>                         cnt_next <= cnt_next + 1;
>                 else
>                         state_next <= state_reg;
>                         cnt_next <= cnt_reg;
>                 end if;
>         end process;
>
>         debounced <= '0' when state_reg=s0 else '1';
> end Behavioral;
>
> Warnings :
> =========================================================================
> *                         Low Level Synthesis                           *
> =========================================================================
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.
>
> What does this mean ?


cnt_next is never registered.

Don't use the two-process state machine description. It leads to
exactly the problem you have.

-a
Reply by Thorsten Kiefer ●April 15, 20082008-04-15
Andy Peters wrote:


> On Apr 15, 8:18 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:
>> Hi,
>> when I synthesize the following, I get warnings.
>>
>> library IEEE;
>> use IEEE.STD_LOGIC_1164.ALL;
>> use ieee.numeric_std.all;
>>
>> ---- Uncomment the following library declaration if instantiating
>> ---- any Xilinx primitives in this code.
>> --library UNISIM;
>> --use UNISIM.VComponents.all;
>>
>> entity debounce is
>>         generic(N : integer := 20);
>>         port(
>>                 clk,reset : in std_logic;
>>                 button : in std_logic;
>>                 debounced : out std_logic
>>         );
>> end debounce;
>>
>> architecture Behavioral of debounce is
>>         type state_type is (s0,s1);
>>         signal state_reg,state_next : state_type;
>>         signal cnt_reg,cnt_next : unsigned(N-1 downto 0);
>> begin
>>         process(clk,reset)
>>         begin
>>                 if reset='1' then
>>                         state_reg <= s0;
>>                         cnt_reg <= (others => '0');
>>                 elsif clk'event and clk='1' then
>>                         state_reg <= state_next;
>>                         cnt_reg <= cnt_next;
>>                 end if;
>>         end process;
>>
>>         process(state_reg,cnt_reg,button)
>>         begin
>>                 if state_reg=s0 and cnt_reg=2**N-1 then
>>                         state_next <= s1;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='0' then
>>                         state_next <= s0;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='1' then
>>                         state_next <= s0;
>>                         cnt_next <= cnt_next + 1;
>>                 elsif state_reg=s1 and cnt_reg=2**N-1 then
>>                         state_next <= s0;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s1 and button='1' then
>>                         state_next <= s1;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s1 and button='0' then
>>                         state_next <= s1;
>>                         cnt_next <= cnt_next + 1;
>>                 else
>>                         state_next <= state_reg;
>>                         cnt_next <= cnt_reg;
>>                 end if;
>>         end process;
>>
>>         debounced <= '0' when state_reg=s0 else '1';
>> end Behavioral;
>>
>> Warnings :
>> =========================================================================
>> *                         Low Level Synthesis                           *
>> =========================================================================
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: N5, cnt_next<0>, cnt_next_share0000<0>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<1>, cnt_next<1>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<2>, cnt_next_share0000<2>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<3>, cnt_next<3>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<4>, cnt_next_share0000<4>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<5>, cnt_next_share0000<5>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<6>, cnt_next_share0000<6>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<7>, cnt_next_share0000<7>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<8>, cnt_next_share0000<8>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<9>, cnt_next_share0000<9>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<10>, cnt_next_share0000<10>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<11>, cnt_next_share0000<11>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<12>, cnt_next_share0000<12>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<13>, cnt_next_share0000<13>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<14>, cnt_next_share0000<14>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<15>, cnt_next_share0000<15>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next<16>, cnt_next_share0000<16>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<17>, cnt_next<17>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<18>, cnt_next<18>.
>> WARNING:Xst:2170 - Unit debounce : the following signal(s) form a
>> combinatorial loop: cnt_next_share0000<19>, cnt_next<19>.
>>
>> What does this mean ?
> 
> cnt_next is never registered.
> 
> Don't use the two-process state machine description. It leads to
> exactly the problem you have.
> 
> -a


Is the a concurrent statement for the next-state-logic better ?
But what if the "next-state logic" becomes more complex ?
Reply by Thorsten Kiefer ●April 15, 20082008-04-15
Kevin Neilson wrote:


> 
>>         process(state_reg,cnt_reg,button)
>>         begin
>>                 if state_reg=s0 and cnt_reg=2**N-1 then
>>                         state_next <= s1;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='0' then
>>                         state_next <= s0;
>>                         cnt_next <= (others=>'0');
>>                 elsif state_reg=s0 and button='1' then
>>                         state_next <= s0;
>>                         cnt_next <= cnt_next + 1;
> 
>> 
> I think the line above shows how the combinatorial loop is formed,
> because you're making a value in a combinatorial process a function of
> itself.  I think what you really want is:
> 
>  >                         cnt_next <= cnt_reg + 1;
> 
> I recommend putting the whole state machine in a single clocked process.
>   It makes the state machine easier to maintain and then you avoid
> having two names for registers and you avoid having combinatorial loops.
>   One side effect is that actions happen not in the named state but
> during the next state.
> -Kevin


can you convert that little example into a single process ?
I have no idea how to do that...
My book says, the state machine has to be separated
into "register/flipflop","next-state logic" and "output logic"
-TK
Reply by Mike Treseler ●April 15, 20082008-04-15
Thorsten Kiefer wrote:


> can you convert that little example into a single process ?


I do it like this:

main : process(reset, clock) is
-- declarations
   begin  -- process template
      if reset = '1' then
         init_regs;
      elsif rising_edge(clock) then
         update_regs;
      end if;
      update_ports;
   end process main;
end architecture synth;

Details here:
http://home.comcast.net/~mike_treseler/

         --Mike Treseler
Reply by Thomas Stanka ●April 16, 20082008-04-16
On 15 Apr., 22:18, Mike Treseler <mike_trese...@comcast.net> wrote:


> main : process(reset, clock) is
> -- declarations
>    begin  -- process template
>       if reset = '1' then
>          init_regs;
>       elsif rising_edge(clock) then
>          update_regs;
>       end if;
>       update_ports;
>    end process main;
> end architecture synth;


This is a good style beside the fact, that a tool i recently use (I
think synopsys dc, not 100% shure) didn't accept the update_ports part
of such an process. Thats why I update ports usualy outside the
process.

bye Thomas
Reply by Mike Treseler ●April 16, 20082008-04-16
Thomas Stanka wrote:

> On 15 Apr., 22:18, Mike Treseler <mike_trese...@comcast.net> wrote:
> 
>> main : process(reset, clock) is
>> -- declarations
>>    begin  -- process template
>>       if reset = '1' then
>>          init_regs;
>>       elsif rising_edge(clock) then
>>          update_regs;
>>       end if;
>>       update_ports;
>>    end process main;
>> end architecture synth;
> 
> This is a good style beside the fact, that a tool i recently use (I
> think synopsys dc, not 100% sure) didn't accept the update_ports part
> of such an process. Thats why I update ports usually outside the
> process.


Thanks for the report.
This style works with quartus, ise, mentor, verific and others.
Updating ports outside the process works also
but I resist adding wires when they are not
logically required.

       -- Mike Treseler