Very simple VHDL problem

Hi there - I am slowly teaching myself VHDL this weekend. I am getting
an error that I do not understand: "parse error, unexpected IF". My
very simple code is at the bottom of this post, and the error is being
caused by the "if switches(0)=0 then" line. Can somebody tell me what
I'm doing wrong? I'm sure it's terribly simple - but coming from a C
background I am having trouble understanding what I'm doing wrong.

Thanks!

-Michael

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hello_world is
port (
	clk, enc_a, end_b : in std_logic;
	switches : in std_logic_vector (3 downto 0);
	led : out std_logic_vector (7 downto 0)
);
end hello_world;

architecture rtl of hello_world is
	signal cnt : std_logic_vector (30 downto 0);
	signal enccnt : std_logic_vector (7 downto 0);
begin
	process(clk)
	begin
		if rising_edge(clk) then
			cnt <= cnt + 1;
		end if;
	end process;

	if switches(0)=0 then
		led <= cnt(30 downto 23);
	else
		led <= enccnt;
	end if;
end rtl;

Michael wrote:

> Hi there - I am slowly teaching myself VHDL this weekend. I am getting
> an error that I do not understand: "parse error, unexpected IF". My
> very simple code is at the bottom of this post, and the error is being
> caused by the "if switches(0)=0 then" line. Can somebody tell me what
> I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> background I am having trouble understanding what I'm doing wrong.

You can't use IF outside of processes, a bit like that you can't use the C
IF outside of functions. You could write it like this:

led <= cnt(30 downto 23) when switches(0)=0 else enccnt;

A bit like the ?-operator in C.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Michael a �crit :
> Hi there - I am slowly teaching myself VHDL this weekend. I am getting
> an error that I do not understand: "parse error, unexpected IF". My
> very simple code is at the bottom of this post, and the error is being
> caused by the "if switches(0)=0 then" line. Can somebody tell me what
> I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> background I am having trouble understanding what I'm doing wrong.

Hello
There are a few points that need clarifying, besides you "unexpected if" 
problem which has already been dealt with.


> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;

NEVER, in any case, use these non-standard libraries called 
std_logic_arith, std_logic_signed and std_logic_unsigned. Use 
numeric_std instead.
With this library, declare your signal cnt as unsigned instead of 
std_logic_vector

[...]
> 
> 	if switches(0)=0 then
> 		led <= cnt(30 downto 23);
> 	else
> 		led <= enccnt;
> 	end if;

Your if statement should be inside a process, as has already been said.
Second point : signal switches is an array of std_logic, not an array of 
integers. std_logic litteral constants must be written betwen single quotes:
if switches(0) = '0' then
   led <= std_logic_vector(led(30 downto 23));

Since cnt is now unsigned, you need to cast it to std_logic_vector 
before assigning to led.

Nicolas

On Apr 19, 10:41=A0pm, Frank Buss <f...@frank-buss.de> wrote:
> Michael wrote:
> > Hi there - I am slowly teaching myself VHDL this weekend. I am getting
> > an error that I do not understand: "parse error, unexpected IF". My
> > very simple code is at the bottom of this post, and the error is being
> > caused by the "if switches(0)=3D0 then" line. Can somebody tell me what
> > I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> > background I am having trouble understanding what I'm doing wrong.
>
> You can't use IF outside of processes, a bit like that you can't use the C=

> IF outside of functions. You could write it like this:
>
> led <=3D cnt(30 downto 23) when switches(0)=3D0 else enccnt;
>
> A bit like the ?-operator in C.

Hi Frank - thanks for clearing that up. I had not realized that
limitation of IF. Why can ifs only be used inside processes? That
strikes me as an odd limitation, though I'm sure there's a good reason
behind it.

I tried your suggestion for the change, but I got this error: "can not
have such operands in this context.". That strikes me as an odd error
- as led, cnt, and enccnt are of the same type.

Any idea what is wrong? Thanks again!

-Michael

On Apr 20, 9:05 am, Michael <nleah...@gmail.com> wrote:
> On Apr 19, 10:41 pm, Frank Buss <f...@frank-buss.de> wrote:
>
> > Michael wrote:
> > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting
> > > an error that I do not understand: "parse error, unexpected IF". My
> > > very simple code is at the bottom of this post, and the error is being
> > > caused by the "if switches(0)=0 then" line. Can somebody tell me what
> > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> > > background I am having trouble understanding what I'm doing wrong.
>
> > You can't use IF outside of processes, a bit like that you can't use the C
> > IF outside of functions. You could write it like this:
>
> > led <= cnt(30 downto 23) when switches(0)=0 else enccnt;
>
> > A bit like the ?-operator in C.
>
> Hi Frank - thanks for clearing that up. I had not realized that
> limitation of IF. Why can ifs only be used inside processes? That
> strikes me as an odd limitation, though I'm sure there's a good reason
> behind it.
>
> I tried your suggestion for the change, but I got this error: "can not
> have such operands in this context.". That strikes me as an odd error
> - as led, cnt, and enccnt are of the same type.
>
> Any idea what is wrong? Thanks again!
>
> -Michael

Hello again - I took Nicholas's suggestion to change the comparison
to: switches(0)='0' (I added single quotes around the 0) - and that
fixed the problem. The code synthesized properly and is now running as
expected on my Spartan-3E dev board! Thanks!

-Michael

Michael wrote:

> Hi Frank - thanks for clearing that up. I had not realized that
> limitation of IF. Why can ifs only be used inside processes? That
> strikes me as an odd limitation, though I'm sure there's a good reason
> behind it.

I don't know if there is a reason, sometimes VHDL looks a bit random to me,
e.g. I always forget where I need a semicolon and where it is forbidden.
Maybe the language designers have designed the IF/WHEN difference, because
IF doesn't need an ELSE, but then you need a latch and WHEN is pure
combinatorial logic.

> I tried your suggestion for the change, but I got this error: "can not
> have such operands in this context.". That strikes me as an odd error
> - as led, cnt, and enccnt are of the same type.

See the other answer: Unlike in C (char/char*) you have to use '0' instead
of just 0 for elements of std_logic_vector (and e.g. "010" for a "string").

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

On Apr 20, 9:05=A0am, Michael <nleah...@gmail.com> wrote:
> On Apr 19, 10:41=A0pm, Frank Buss <f...@frank-buss.de> wrote:
>
> > Michael wrote:
> > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting=

> > > an error that I do not understand: "parse error, unexpected IF". My
> > > very simple code is at the bottom of this post, and the error is being=

> > > caused by the "if switches(0)=3D0 then" line. Can somebody tell me wha=
t
> > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> > > background I am having trouble understanding what I'm doing wrong.
>
> > You can't use IF outside of processes, a bit like that you can't use the=
 C
> > IF outside of functions. You could write it like this:
>
> > led <=3D cnt(30 downto 23) when switches(0)=3D0 else enccnt;
>
> > A bit like the ?-operator in C.
>
> Hi Frank - thanks for clearing that up. I had not realized that
> limitation of IF. Why can ifs only be used inside processes? That
> strikes me as an odd limitation, though I'm sure there's a good reason
> behind it.
>
> I tried your suggestion for the change, but I got this error: "can not
> have such operands in this context.". That strikes me as an odd error
> - as led, cnt, and enccnt are of the same type.
>
> Any idea what is wrong? Thanks again!
>
> -Michael

Hello again - I took Nicholas's suggestion and put single quotes
around the '0' in the switches(0)=3D'0' comparison - and now it works
exactly as expected! Thanks!

-Michael

On Apr 20, 6:37=A0am, Nicolas Matringe <nicolas.matri...@fre.fre> wrote:
> Michael a =E9crit :
>
> > Hi there - I am slowly teaching myself VHDL this weekend. I am getting
> > an error that I do not understand: "parse error, unexpected IF". My
> > very simple code is at the bottom of this post, and the error is being
> > caused by the "if switches(0)=3D0 then" line. Can somebody tell me what
> > I'm doing wrong? I'm sure it's terribly simple - but coming from a C
> > background I am having trouble understanding what I'm doing wrong.
>
> Hello
> There are a few points that need clarifying, besides you "unexpected if"
> problem which has already been dealt with.
>
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> NEVER, in any case, use these non-standard libraries called
> std_logic_arith, std_logic_signed and std_logic_unsigned. Use
> numeric_std instead.
> With this library, declare your signal cnt as unsigned instead of
> std_logic_vector

Hi Nicholas! I must admit I did not make a conscious choice to use
those libraries - they were put in automatically by Xilinx ISE. So
you're saying for my purposes, that section should just look like
this?:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

> [...]
>
>
>
> > =A0 =A0if switches(0)=3D0 then
> > =A0 =A0 =A0 =A0 =A0 =A0led <=3D cnt(30 downto 23);
> > =A0 =A0else
> > =A0 =A0 =A0 =A0 =A0 =A0led <=3D enccnt;
> > =A0 =A0end if;
>
> Your if statement should be inside a process, as has already been said.
> Second point : signal switches is an array of std_logic, not an array of
> integers. std_logic litteral constants must be written betwen single quote=
s:
> if switches(0) =3D '0' then
> =A0 =A0led <=3D std_logic_vector(led(30 downto 23));

Ah - perfect! Adding those quotes just fixed one of my problems!

> Since cnt is now unsigned, you need to cast it to std_logic_vector
> before assigning to led.
>
> Nicolas

So is a cast in VHDL just like a cast in C? I must admit this is the
first I've heard of VHDL having that ability.

Thanks!

-Michael

Hi Michael,
This might help you...
Cheers, Syms.
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf 

Frank Buss wrote:
(snip)

> You can't use IF outside of processes, a bit like that you can't use the C
> IF outside of functions. You could write it like this:

> led <= cnt(30 downto 23) when switches(0)=0 else enccnt;

> A bit like the ?-operator in C.

If you use verilog, the ?: operator is just like the C operator!

-- glen