DCM configuration in Virtex-4 FPGA

Hi all,

I'm having a little problem to implement a DCM. It's the first time i
need it (to be able to use DDR SDRAM).
Before i'm going to think about a design for a memory controller, i
first want to verify that i'm able to control a DCM. I've read a lot
of datasheets, and think i know the theory. In ISE 9.2i i added an IP
for a DCM which is easy to configure. To test if my configuration is
right, i want to measure these clocks by using the DIFF CLK OUT pins
(SMA connectors).
The only problem is that i have no idee which pins belong to the
DCM...and don't know how to connect the DCM's clock outputs to the
DIFF CLK output-pins in order to measure them.
So if anybody could tell me which bank and pin-number belongs to the
DCM(s) i would be very happy :)

Greetz,
  Mr.M

<mspiegels@gmail.com> wrote in message 
news:ba79fdd6-bd77-4b2c-a1a8-b2253055a564@x19g2000prg.googlegroups.com...
>
> The only problem is that i have no idee which pins belong to the
> DCM...and don't know how to connect the DCM's clock outputs to the
> DIFF CLK output-pins in order to measure them.
> So if anybody could tell me which bank and pin-number belongs to the
> DCM(s) i would be very happy :)
>

There are no pins belonging to DCMs. There are pins dedicated as clock 
inputs though. Usually pin assignments are handled in the project's UCF 
file. For your differential output you need to instantiate a differential 
driver in your HDL code and assign the pins in the UCF.. Driving clock out 
of the chip is better done with a DDR register in IOB, but this is another 
issue, probably not important for you at this point.


/Mikhail

MM,

You decide where to put the pins.

Input clocks to the DCM should come from the global clock IO pins (those
IBUFG routes are optimized for 0 delay).

Output clocks should go to a BUFG where they can get used by the things
that need them.

If you wish to observe a clock, route the BUFG to a IOB, set the IOB to
be a DDR, set the top DFF D input to '1', and the bottom DFF D input to
a '0'.

This preserves the duty cycle to within a few tens of ps, and you may
then see exactly what your clock is doing.

Using a differential output standard, and measuring the output
differentially will allow you to see the jitter on the internal BUFG,
excluding any ground or Vcc bounce (as the differential output and
differential measurement ignores common mode changes!).

The CLOCK_FB (feedback clock) to the DCM should always come from the
source which you are trying to align to create 0 skew: ie. the output
BUFG itself, or if that output is sent off-chip, another global clock
input pins (IBUFG)-- 0 skew is created at the point where the clock is
delivered off-chip..

Austin

MM wrote:
> <mspiegels@gmail.com> wrote in message 
> news:ba79fdd6-bd77-4b2c-a1a8-b2253055a564@x19g2000prg.googlegroups.com...
>> The only problem is that i have no idee which pins belong to the
>> DCM...and don't know how to connect the DCM's clock outputs to the
>> DIFF CLK output-pins in order to measure them.
>> So if anybody could tell me which bank and pin-number belongs to the
>> DCM(s) i would be very happy :)
>>
> 
> There are no pins belonging to DCMs. There are pins dedicated as clock 
> inputs though. Usually pin assignments are handled in the project's UCF 
> file. For your differential output you need to instantiate a differential 
> driver in your HDL code and assign the pins in the UCF.. Driving clock out 
> of the chip is better done with a DDR register in IOB, but this is another 
> issue, probably not important for you at this point.
> 
> 
> /Mikhail
> 
> 
> 
> 

Heey Austin and Mikhail,

Thanks for the replies, it's still a bit difficult for me to make sens
of it all because i have to learn more about these "buffers" (IBUFG
and BUFG) but some more research on the internet will probably do the
trick. It's clear now that these DCM's are internal and no physical
pins are involved. A little fight with ISE to get the DCM IP-block
work will be needed :)
Offcourse if anyone has made a little program with a DCM involved, any
code of how it's implemented is welcome.
Once again: thanks!

Mr.M

<mspiegels@gmail.com> wrote in message 
news:158c50e1-7947-4c77-80a8-b887eab3e267@z72g2000hsb.googlegroups.com...
> Heey Austin and Mikhail,
>
> Thanks for the replies, it's still a bit difficult for me to make sens
> of it all because i have to learn more about these "buffers" (IBUFG
> and BUFG) but some more research on the internet will probably do the
> trick. It's clear now that these DCM's are internal and no physical
> pins are involved. A little fight with ISE to get the DCM IP-block
> work will be needed :)
> Offcourse if anyone has made a little program with a DCM involved, any
> code of how it's implemented is welcome.
> Once again: thanks!

It is all in the documentation for the tools and for the chips. Internet 
research is not required. DCM IP block is very easy to get to work. However, 
perhaps before going there you should acquire some more basic skills of 
working with the tools. Learn how to do a LED flasher or something like 
that... Then add a DCM in it...


/Mikhail