Multiple PicoBlaze/Bus access

My design has 2 PicoBlaze processors on a Spartan-IIE sharing a common
IO bus (PORT_ID, IN_PORT, OUT_PORT, READ_STROBE, WRITE_STROBE). I am
planning to use simple priority based bus arbitration. Now I am trying
to figure out the minimal changes I need make to the PicoBlaze core in
order for the IO logic to be bus aware. It needs to assert BREQ to
request the bus, wait until BACK, use the bus, then deassert BREQ to
release the bus.

Any suggestions are most appreciated. Any resources I can look at?

Thanks,

- Abdul

In article <c204a8fb.0402191232.14222631@posting.google.com>,
 abduln@gte.net (Abdul Nizar) writes:
>My design has 2 PicoBlaze processors on a Spartan-IIE sharing a common
>IO bus (PORT_ID, IN_PORT, OUT_PORT, READ_STROBE, WRITE_STROBE). I am
>planning to use simple priority based bus arbitration. Now I am trying
>to figure out the minimal changes I need make to the PicoBlaze core in
>order for the IO logic to be bus aware. It needs to assert BREQ to
>request the bus, wait until BACK, use the bus, then deassert BREQ to
>release the bus.

If the bus is simple (as in a single cycle per operation), another
approach is to alternate between CPUs and make each CPU stall if
it needs the bus at the wrong time.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.