Performance of STAPL player on embedded systems

Started by Rienk van der Scheer August 13, 2003
I there anyone who implemented Altera's STAPL bytecode player on an 
embedded system (say 16-bit microcontroller) to program large FPGAs and 

It seems that especially the bitshift operations are programmed very 
ineffiently, resulting in a performance worse than needed.
The .jbc files generated by Quartus 3 are reasonable efficient for FPGAs 
because they only execute a single DRSCAN operation. But the .jbc files 
generated for programming enhanced EPC devices seem to be terrible: many 
separate DRSCAN operations and bitshifts. Programming an EPC4 from a PC 
is done in less than 2 minutes, but programming it with our Coldfire 
5272 takes about 10 minutes.
Anyone with the same or other experiences?