Call VHDL module from Verilog

Hi,

 I have a basic question.  Is is possible in the xilinx ISE enviroment
to make a verilog wrapper of some VHDL code.  I don't want to recode
it in verilog.

Thanks
Rob

On May 6, 3:38=A0pm, egadget1 <rnu...@gmail.com> wrote:
> Hi,
>
> =A0I have a basic question. =A0Is is possible in the xilinx ISE enviroment=

> to make a verilog wrapper of some VHDL code. =A0I don't want to recode
> it in verilog.
>
> Thanks
> Rob

Never mine I figured it out.

Rob

egadget1 wrote:

>>  I have a basic question.  Is is possible in the xilinx ISE enviroment
>> to make a verilog wrapper of some VHDL code.  I don't want to recode
>> it in verilog.
>>
>> Thanks
>> Rob
> 
> Never mind I figured it out.

The rule is, you have to tell us what you did ;)