Hi, I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to one of the GCLK pins of the Spartan 3 FPGA? Should I put a current limiting resistor in the clock path before I feed it to the GCLK pin? Any issues with that? Best Wishes, Farhan
5 V oscillator output to GCLK
Started by ●May 9, 2008
Reply by ●May 9, 20082008-05-09
On Fri, 9 May 2008 01:01:45 -0700 (PDT), maverick <sheikh.m.farhan@gmail.com> wrote:>Hi, >I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator >which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL >mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to >one of the GCLK pins of the Spartan 3 FPGA? Should I put a current >limiting resistor in the clock path before I feed it to the GCLK pin? >Any issues with that?Better to use a resistive divider to (a) drop the 5V to 3.3V and (b) match the impedance of the signal trace. My preference would be for series termination, i.e. place the resistive divider at the oscillator end, assuming the clk trace is a simple trace (no major stubs feeding different destinations). If the oscillator can't drive such a low impedance, you need a higher impedance divider. Then I would place it aas close as possible to the Spartan pin. - Brian
Reply by ●May 9, 20082008-05-09
On 9 Mai, 14:23, Brian Drummond <brian_drumm...@btconnect.com> wrote:> My preference would be for > series termination, i.e. place the resistive divider at the oscillator > end, assuming the clk trace is a simple traceDo both: One resistor in series at the source, one resistor to ground at the destination. You get a transmission line that is terminated at both ends. A reflection caused by a mismatch at the destination is dampened at the source. This provides essentially the best signal quality you can get. The only disadvantage is the reduced swing at the destination. But this is exactly what the OP wants. Kolja Sulimma
Reply by ●May 9, 20082008-05-09
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:0d885ecd-0839-416b-98fd-1ff4f1835806@34g2000hsh.googlegroups.com...> On 9 Mai, 14:23, Brian Drummond <brian_drumm...@btconnect.com> wrote: >> My preference would be for >> series termination, i.e. place the resistive divider at the oscillator >> end, assuming the clk trace is a simple trace > > Do both: > One resistor in series at the source, one resistor to ground at the > destination. > You get a transmission line that is terminated at both ends. A > reflection caused > by a mismatch at the destination is dampened at the source. > > This provides essentially the best signal quality you can get. The > only disadvantage > is the reduced swing at the destination. But this is exactly what the > OP wants. > > Kolja SulimmaA better solution would be to feed the clock through a 3.3V buffer that is 5V tolerant. An AHC family device would do the job I think. In fact, a 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin package.
Reply by ●May 9, 20082008-05-09
On May 9, 11:53=A0am, "David Spencer" <davidmspen...@verizon.net> wrote:> > A better solution would be to feed the clock through a 3.3V buffer that is=> 5V tolerant. An AHC family device would do the job I think. In fact, a > 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin > package.- Hide quoted text - >By what measure would an IC be a "better solution" than two resistors? KJ
Reply by ●May 9, 20082008-05-09
maverick wrote:> Hi, > I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator > which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL > mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to > one of the GCLK pins of the Spartan 3 FPGA? Should I put a current > limiting resistor in the clock path before I feed it to the GCLK pin? > Any issues with that? > > Best Wishes, > FarhanI just got a 3.3V oscillator driving a 2.5V input working. The oscillator has miserable drive capability and I suspect the 5V oscillator you're using may have poor drive capability as well. Unless you have a rare high-drive oscillator OR if you're oscillating at a leisurely rate, do like the FPGA vendor recommends: use a 100 ohm series resistor. If you use a resistor divider, your parasitics can severely slow down your edges. Our 125 MHz oscillator looked almost like a sine wave and was reduced in amplitude to the point we were getting 25% duty cycle. Not good for our application. If it was a 20 MHz oscillator, the resitor divider would probably be fine. If we could deal with 25% duty cycle we could have probably used what was there. The series resistor just plain works. The input protection on the Spartan3 is pretty robust so you can drive the many milliamps (if you have many milliamps) into the protection diode without affecting reliability. If I wanted to be detailed, I'd understand the drive capability, the frequency, and the parasitics involved. - John_H
Reply by ●May 9, 20082008-05-09
John_H wrote:> maverick wrote: > >>Hi, >>I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator >>which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL >>mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to >>one of the GCLK pins of the Spartan 3 FPGA? Should I put a current >>limiting resistor in the clock path before I feed it to the GCLK pin? >>Any issues with that? >> >>Best Wishes, >>Farhan > > > I just got a 3.3V oscillator driving a 2.5V input working. The > oscillator has miserable drive capability and I suspect the 5V > oscillator you're using may have poor drive capability as well. > > Unless you have a rare high-drive oscillator OR if you're oscillating > at a leisurely rate, do like the FPGA vendor recommends: use a 100 ohm > series resistor. > > If you use a resistor divider, your parasitics can severely slow down > your edges. Our 125 MHz oscillator looked almost like a sine wave and > was reduced in amplitude to the point we were getting 25% duty cycle. > Not good for our application. If it was a 20 MHz oscillator, the > resitor divider would probably be fine. If we could deal with 25% > duty cycle we could have probably used what was there. The series > resistor just plain works. The input protection on the Spartan3 is > pretty robust so you can drive the many milliamps (if you have many > milliamps) into the protection diode without affecting reliability. > > If I wanted to be detailed, I'd understand the drive capability, the > frequency, and the parasitics involved.Or, think like a scope probe, and do a capacitive divider, That preserves the edges, and allows higher value resistors (so saves power) Measure the pin/pcb capacitance, and Osc output swing, and then calculate the driving capacitance, likely to be in tne 30-40pF region. Or, add a LVC1G57/58/97/98 to your parts list, and use that. -jg
Reply by ●May 9, 20082008-05-09
"KJ" <kkjennings@sbcglobal.net> wrote in message news:cf46e434-c521-4155-ab4a-efcd7587c41f@27g2000hsf.googlegroups.com...>On May 9, 11:53 am, "David Spencer" <davidmspen...@verizon.net> wrote:> >> A better solution would be to feed the clock through a 3.3V buffer that >> is >> 5V tolerant. An AHC family device would do the job I think. In fact, a >> 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin >> package.- Hide quoted text - >> By what measure would an IC be a "better solution" than two resistors?> KJStatic drive current. Assuming the divider is matched to the impedance of the trace, as originally suggested, the oscillator would need to source and sink around 100 mA.
Reply by ●May 9, 20082008-05-09
KJ wrote:> On May 9, 11:53 am, "David Spencer" <davidmspen...@verizon.net> wrote: > > >>A better solution would be to feed the clock through a 3.3V buffer that is >>5V tolerant. An AHC family device would do the job I think. In fact, a >>74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin >>package.- Hide quoted text - >> > > > By what measure would an IC be a "better solution" than two resistors?You don't want slow clock transitions, and high drive impedances at the receiving end. Now, the right choice of resistors probably won't cause such trouble, but it at least needs to be considered. A long clock trace (bad idea, anyway) fed with a series resistor is essentially a lumped-constant low-pass filter. I'm not sure how fast Spartan III is, but if the Tr got slowed to tens of nS it would be really dangerous. Just add a little on-chip or on-board noise, and you have extra clock transitions. I've seen this on a 5V Spartan setup that got its clock from an LVDS receiver. Some reflections on the LVDS cable caused multiple clocks that the Spartan FFs responded to. I'm sure this would only be more sensitive on Spartan 3. I just did a board that had a bunch of logic turned upside down (-5 V and ground) and used resistive networks with matching caps across the series resistor to keep the edges sharp. This had to be done some 70 places on the board, and there's no suitable chip for such a conversion. It worked, but had me sweating until proven. Jon
Reply by ●May 9, 20082008-05-09
On May 9, 1:51=A0pm, "David Spencer" <davidmspen...@verizon.net> wrote:> "KJ" <kkjenni...@sbcglobal.net> wrote in message > > news:cf46e434-c521-4155-ab4a-efcd7587c41f@27g2000hsf.googlegroups.com... > > >On May 9, 11:53 am, "David Spencer" <davidmspen...@verizon.net> wrote: > > >> A better solution would be to feed the clock through a 3.3V buffer that=> >> is > >> 5V tolerant. An AHC family device would do the job I think. In fact, a > >> 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin > >> package.- Hide quoted text - > > > By what measure would an IC be a "better solution" than two resistors? > > KJ > > Static drive current. > > Assuming the divider is matched to the impedance of the trace, as original=ly> suggested, the oscillator would need to source and sink around 100 mA.Make that 50 mA, if the series resistor is 50 Ohm, and the parallel destination termination another 50 Ohm. Peter Alfke
