5 V oscillator output to GCLK

"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message 
news:48255f20@clear.net.nz...
> Peter Alfke wrote:
>
>> So let's reduce the series resistor at the source to 25 Ohm, and keep
>> the parallel termination at the destination at 50 Ohm.
>> That puts 2/3 of Vcc on the cable and the FPGA input = 3.3 V. The 25
>> Ohm includes the drive impedance, which might mean no external series
>> resistor at all...
>> Peter
>
> Yes, that would work, However....
>
> # You are no longer doing strict series-impedance-match termination
> # One can tell you are used to high-power FPGAs ;)

Oscillators typically can't drive 50 ohms impedances either so impedance 
matching to the PCB would not be relevant....the optimal solution would be a 
series resistor of  ~1.75x - 2x, parallel to ground of 3x where 'x' needs to 
be determined based on the spec'ed drive capability of the oscillator.  An 
IBIS or Spice model would determine 'x'.  Assuming the osc to be 50MHz or 
less, a PCB impedance of ~50 ohms, I'd suspect that x ~ 50-75 would give 
good signal quality and meet Vih requirements at the FPGA.

>  - as this sugestion adds a cost of 33mA in power budget (@50% clk duty 
> cycle).
>
> Suppose the target was a Zero power CPLD ?
> The whole device Icc might be 14.6mA at 200Mhz - 7.5mA @ 100MHz.
> [OP did not mention speed, but 5V sources are << 100Mhz ]
>
> The clock-terminator is consuming far more power than the CPLD !
>

If power consumption was even remotely close to the case that the OP was has 
in mind he wouldn't bother with any of this...he would've replaced the 5V 
osc with a 3.3V one.  Presumably there is some reason for even wanting to 
have a 5V osc on the board in the first place, but minimizing power 
consumption is not the reason.

Kevin Jennings 

Correction to previous post.  I'd suspect 'x' to be ~25-40, not 50-75.

KJ 

On May 10, 1:37=A0am, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Peter Alfke wrote:
> > On May 9, 7:57 pm, Jim Granville <no.s...@designtools.maps.co.nz>
> > wrote:
>
> >>Peter Alfke wrote:
>
> >>>On May 9, 5:19 pm, Jim Granville <no.s...@designtools.maps.co.nz>
> >>>wrote:
>
> >>>>Peter Alfke wrote:
>
> >>>>>When you series-terminate the driver, and parallel-terminate the
> >>>>>receiver, each with a resistor that equals the characteristic
> >>>>>impedance of the clock trace, then a fast transition sees just a
> >>>>>resistive divider, not a lumped capacitance.
> >>>>>That's the beauty of terminated transmission lines...
>
> >>>>That's true, until it bangs into the lumped input capacitance of the
> >>>>FPGA.
> >>>>You also get a voltage-loss with this focus on transmission
> >>>>line matching, which might give noise margin issues, as
> >>>>well as Buffer Current adders, from the lower Vih.
>
> >>>>-jg
>
> >>>Let's not forget: "Voltage loss" was the purpose of the whole
> >>>exercise...
> >>>Peter
>
> >>I should have been clearer :
> >>Equal Source/Load terminations will turn the 5V swing into 2.5V Hi, on a=

> >>3.3V system.
> >>The ideal Vih is 3.3V, (lowest power, best noise immunity), so this
> >>is a lower Vih, which was the 'voltage loss' I was getting at.
>
> >>-jg
>
> > So let's reduce the series resistor at the source to 25 Ohm, and keep
> > the parallel termination at the destination at 50 Ohm.
> > That puts 2/3 of Vcc on the cable and the FPGA input =3D 3.3 V. The 25
> > Ohm includes the drive impedance, which might mean no external series
> > resistor at all...
> > Peter
>
> Yes, that would work, However....
>
> # You are no longer doing strict series-impedance-match termination
> # One can tell you are used to high-power FPGAs ;)
> =A0 - as this sugestion adds a cost of 33mA in power budget (@50% clk duty=

> cycle).
>
> Suppose the target was a Zero power CPLD ?
> The whole device Icc might be 14.6mA at 200Mhz - 7.5mA @ 100MHz.
> [OP did not mention speed, but 5V sources are << 100Mhz ]
>
> The clock-terminator is consuming far more power than the CPLD !
>
> -jg

Just to belabor a point: When the output side of a transmission line
is parallel-terminated, there is no requirement to also properly
terminate the driving side. Using a "wrong" series resistor to adjust
the amplitude is ok, since there is no signal coming back to the
driver, and thus no need for proper termination at that end.
Peter Alfke

On 9 Mai, 23:33, Jon Elson <el...@wustl.edu> wrote:
>  A long clock trace (bad idea, anyway) fed with a series resistor is essentially
> a lumped-constant low-pass filter.

No. It is a transmission line with an impedance matched driver. You
can get any
frequency accross that setup that you like.


>  I'm not sure how fast Spartan III
> is, but if the Tr got slowed to tens of nS it would be really dangerous.

The setup will not change the rise time of the signal. The slew rate
will be halved,
because the voltage swing is halved, but that's it.
The receiver will see the same waveform as the source with halve the
voltage.

But other posters where correct with noting that the oscillator needs
to be capable
to drive a 100R transmission line, which might not be the case.

Kolja Sulimma

Kolja Sulimma wrote:

> On 9 Mai, 23:33, Jon Elson <el...@wustl.edu> wrote:

>> A long clock trace (bad idea, anyway) fed with a series
>> resistor is essentially a lumped-constant low-pass filter.

> No. It is a transmission line with an impedance matched driver. 
> You can get any frequency accross that setup that you like.

If matched with the characteristic impedance it works
like a transmission line, if not it looks like a capacitor
or inductor depending on the termination.

The phone system (US, anyway) seems to use 600 ohm termination
on about 100 ohm UTP cable.  The result is that the cable looks
like a capacitor and, for long lines, results in a high frequency
drop off.

http://en.wikipedia.org/wiki/Loading_coil

The telephone solution is loading coils that increase the
series inductance (on average) resulting in a flatter
response to the required 4kHz, and a sharp drop after that.

The effect also shows up in antenna design when the frequency
doesn't match the appropriate length for the antenna elements.

As previously stated, though, it is only necessary to match
one end.  If the sink impedance is matched the voltage will
be reduced appropriately by the series source resistor
and the cable impedance as a voltage divider.

-- glen