xilinx beginner modelsim question

Hi!!!

I started recently with the xilinx software and these days I am trying
to become more familiar with the modelsim and ise. I  wanted to test
some basic counter simulation in modelsim so I used this simple code

counter design file

library ieee ;
  use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;

  entity counter is
   port(  clk:  in std_logic;
     reset:  in std_logic;
     enable:  in std_logic;
     count:  out std_logic_vector(3 downto 0)
  );
  end counter;

  architecture behav of counter is
    signal pre_count: std_logic_vector(3 downto 0);
    begin
      process(clk, enable, reset)
      begin
        if reset = '1' then
          pre_count <= "0000";
       elsif (clk='1' and clk'event) then
          if enable = '1' then
           pre_count <= pre_count + "1";
          end if;
        end if;
      end process;
      count <= pre_count;
  end behav;


testbench


  library ieee ;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_textio.all;
  use std.textio.all;

  entity counter_tb is
  end;

  architecture counter_tb of counter_tb is

 component counter
   port ( count : out std_logic_vector(3 downto 0);
          clk   : in std_logic;
          enable: in std_logic;
          reset : in std_logic);
 end component ;

 signal   clk    : std_logic := '0';
 signal   reset  : std_logic := '0';
 signal   enable : std_logic := '0';
 signal   count  : std_logic_vector(3 downto 0);

 begin

  dut : counter
 port map (
     count => count,
     clk   => clk,
    enable=> enable,
    reset => reset );


   clock : process
   begin
       clk<='0';
       wait for 5 ns;
       clk<='1';
       wait for 5 ns;
   end process clock;

   stimulus : process
   begin

     wait for 5 ns; reset  <= '1';
      wait for 4 ns; reset  <= '0';
      wait for 4 ns; enable <= '1';
    wait;
  end process stimulus;

but my simulation doesn't give right results. (I am getting U state on
all inputs). I am trying to find my mistake for more than 4 hours so
please if someone could help me please do it. I have defined new
project, I have compiled files and when I start simulation this
results repeat over and over again. I fell that this is stupid little
mistake but I can't find it no matter  what.

Thanks for any kind of help
Zoran

On May 14, 5:09=A0am, Zorjak <Zor...@gmail.com> wrote:
> Hi!!!
>
> I started recently with the xilinx software and these days I am trying
> to become more familiar with the modelsim and ise. I =A0wanted to test
> some basic counter simulation in modelsim so I used this simple code
>
> counter design file
>
> library ieee ;
> =A0 use ieee.std_logic_1164.all;
> =A0 =A0use ieee.std_logic_unsigned.all;
>
> =A0 entity counter is
> =A0 =A0port( =A0clk: =A0in std_logic;
> =A0 =A0 =A0reset: =A0in std_logic;
> =A0 =A0 =A0enable: =A0in std_logic;
> =A0 =A0 =A0count: =A0out std_logic_vector(3 downto 0)
> =A0 );
> =A0 end counter;
>
> =A0 architecture behav of counter is
> =A0 =A0 signal pre_count: std_logic_vector(3 downto 0);
> =A0 =A0 begin
> =A0 =A0 =A0 process(clk, enable, reset)
> =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 if reset =3D '1' then
> =A0 =A0 =A0 =A0 =A0 pre_count <=3D "0000";
> =A0 =A0 =A0 =A0elsif (clk=3D'1' and clk'event) then
> =A0 =A0 =A0 =A0 =A0 if enable =3D '1' then
> =A0 =A0 =A0 =A0 =A0 =A0pre_count <=3D pre_count + "1";
> =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 end process;
> =A0 =A0 =A0 count <=3D pre_count;
> =A0 end behav;
>
> testbench
>
> =A0 library ieee ;
> =A0 use ieee.std_logic_1164.all;
> =A0 use ieee.std_logic_unsigned.all;
> =A0 use ieee.std_logic_textio.all;
> =A0 use std.textio.all;
>
> =A0 entity counter_tb is
> =A0 end;
>
> =A0 architecture counter_tb of counter_tb is
>
> =A0component counter
> =A0 =A0port ( count : out std_logic_vector(3 downto 0);
> =A0 =A0 =A0 =A0 =A0 clk =A0 : in std_logic;
> =A0 =A0 =A0 =A0 =A0 enable: in std_logic;
> =A0 =A0 =A0 =A0 =A0 reset : in std_logic);
> =A0end component ;
>
> =A0signal =A0 clk =A0 =A0: std_logic :=3D '0';
> =A0signal =A0 reset =A0: std_logic :=3D '0';
> =A0signal =A0 enable : std_logic :=3D '0';
> =A0signal =A0 count =A0: std_logic_vector(3 downto 0);
>
> =A0begin
>
> =A0 dut : counter
> =A0port map (
> =A0 =A0 =A0count =3D> count,
> =A0 =A0 =A0clk =A0 =3D> clk,
> =A0 =A0 enable=3D> enable,
> =A0 =A0 reset =3D> reset );
>
> =A0 =A0clock : process
> =A0 =A0begin
> =A0 =A0 =A0 =A0clk<=3D'0';
> =A0 =A0 =A0 =A0wait for 5 ns;
> =A0 =A0 =A0 =A0clk<=3D'1';
> =A0 =A0 =A0 =A0wait for 5 ns;
> =A0 =A0end process clock;
>
> =A0 =A0stimulus : process
> =A0 =A0begin
>
> =A0 =A0 =A0wait for 5 ns; reset =A0<=3D '1';
> =A0 =A0 =A0 wait for 4 ns; reset =A0<=3D '0';
> =A0 =A0 =A0 wait for 4 ns; enable <=3D '1';
> =A0 =A0 wait;
> =A0 end process stimulus;
>
> but my simulation doesn't give right results. (I am getting U state on
> all inputs). I am trying to find my mistake for more than 4 hours so
> please if someone could help me please do it. I have defined new
> project, I have compiled files and when I start simulation this
> results repeat over and over again. I fell that this is stupid little
> mistake but I can't find it no matter =A0what.
>
> Thanks for any kind of help
> Zoran

Zoran -

I compiled and simulated your files in Modelsim SE 6.2h and your
counter works fine.  Perhaps you should try some of the examples that
ship with Modelsim - find the examples folder in your install
directory.  Maybe something is wrong in your modelsim.ini file; I
really have no idea.

Barry

On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote:
> Hi!!!
>
> I started recently with the xilinx software and these days I am trying
> to become more familiar with the modelsim and ise. I  wanted to test
> some basic counter simulation in modelsim so I used this simple code
>
> counter design file
>
> library ieee ;
>   use ieee.std_logic_1164.all;
>    use ieee.std_logic_unsigned.all;
>
>   entity counter is
>    port(  clk:  in std_logic;
>      reset:  in std_logic;
>      enable:  in std_logic;
>      count:  out std_logic_vector(3 downto 0)
>   );
>   end counter;
>
>   architecture behav of counter is
>     signal pre_count: std_logic_vector(3 downto 0);
>     begin
>       process(clk, enable, reset)
>       begin
>         if reset = '1' then
>           pre_count <= "0000";
>        elsif (clk='1' and clk'event) then
>           if enable = '1' then
>            pre_count <= pre_count + "1";
>           end if;
>         end if;
>       end process;
>       count <= pre_count;
>   end behav;
>
> testbench
>
>   library ieee ;
>   use ieee.std_logic_1164.all;
>   use ieee.std_logic_unsigned.all;
>   use ieee.std_logic_textio.all;
>   use std.textio.all;
>
>   entity counter_tb is
>   end;
>
>   architecture counter_tb of counter_tb is
>
>  component counter
>    port ( count : out std_logic_vector(3 downto 0);
>           clk   : in std_logic;
>           enable: in std_logic;
>           reset : in std_logic);
>  end component ;
>
>  signal   clk    : std_logic := '0';
>  signal   reset  : std_logic := '0';
>  signal   enable : std_logic := '0';
>  signal   count  : std_logic_vector(3 downto 0);
>
>  begin
>
>   dut : counter
>  port map (
>      count => count,
>      clk   => clk,
>     enable=> enable,
>     reset => reset );
>
>    clock : process
>    begin
>        clk<='0';
>        wait for 5 ns;
>        clk<='1';
>        wait for 5 ns;
>    end process clock;
>
>    stimulus : process
>    begin
>
>      wait for 5 ns; reset  <= '1';
>       wait for 4 ns; reset  <= '0';
>       wait for 4 ns; enable <= '1';
>     wait;
>   end process stimulus;
>
> but my simulation doesn't give right results. (I am getting U state on
> all inputs). I am trying to find my mistake for more than 4 hours so
> please if someone could help me please do it. I have defined new
> project, I have compiled files and when I start simulation this
> results repeat over and over again. I fell that this is stupid little
> mistake but I can't find it no matter  what.
>
> Thanks for any kind of help
> Zoran

Your clock process will only produce -1- clock cycle.  You need the
clock to be in a loop:

   clock : process
   begin
     loop
       clk<='0';
       wait for 5 ns;
       clk<='1';
       wait for 5 ns;
     end loop;
   end process clock;

-Dave Pollum

On May 14, 11:47 am, Dave Pollum <vze24...@verizon.net> wrote:
> On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote:
>
>
>
> > Hi!!!
>
> > I started recently with the xilinx software and these days I am trying
> > to become more familiar with the modelsim and ise. I  wanted to test
> > some basic counter simulation in modelsim so I used this simple code
>
> > counter design file
>
> > library ieee ;
> >   use ieee.std_logic_1164.all;
> >    use ieee.std_logic_unsigned.all;
>
> >   entity counter is
> >    port(  clk:  in std_logic;
> >      reset:  in std_logic;
> >      enable:  in std_logic;
> >      count:  out std_logic_vector(3 downto 0)
> >   );
> >   end counter;
>
> >   architecture behav of counter is
> >     signal pre_count: std_logic_vector(3 downto 0);
> >     begin
> >       process(clk, enable, reset)
> >       begin
> >         if reset = '1' then
> >           pre_count <= "0000";
> >        elsif (clk='1' and clk'event) then
> >           if enable = '1' then
> >            pre_count <= pre_count + "1";
> >           end if;
> >         end if;
> >       end process;
> >       count <= pre_count;
> >   end behav;
>
> > testbench
>
> >   library ieee ;
> >   use ieee.std_logic_1164.all;
> >   use ieee.std_logic_unsigned.all;
> >   use ieee.std_logic_textio.all;
> >   use std.textio.all;
>
> >   entity counter_tb is
> >   end;
>
> >   architecture counter_tb of counter_tb is
>
> >  component counter
> >    port ( count : out std_logic_vector(3 downto 0);
> >           clk   : in std_logic;
> >           enable: in std_logic;
> >           reset : in std_logic);
> >  end component ;
>
> >  signal   clk    : std_logic := '0';
> >  signal   reset  : std_logic := '0';
> >  signal   enable : std_logic := '0';
> >  signal   count  : std_logic_vector(3 downto 0);
>
> >  begin
>
> >   dut : counter
> >  port map (
> >      count => count,
> >      clk   => clk,
> >     enable=> enable,
> >     reset => reset );
>
> >    clock : process
> >    begin
> >        clk<='0';
> >        wait for 5 ns;
> >        clk<='1';
> >        wait for 5 ns;
> >    end process clock;
>
> >    stimulus : process
> >    begin
>
> >      wait for 5 ns; reset  <= '1';
> >       wait for 4 ns; reset  <= '0';
> >       wait for 4 ns; enable <= '1';
> >     wait;
> >   end process stimulus;
>
> > but my simulation doesn't give right results. (I am getting U state on
> > all inputs). I am trying to find my mistake for more than 4 hours so
> > please if someone could help me please do it. I have defined new
> > project, I have compiled files and when I start simulation this
> > results repeat over and over again. I fell that this is stupid little
> > mistake but I can't find it no matter  what.
>
> > Thanks for any kind of help
> > Zoran
>
> Your clock process will only produce -1- clock cycle.  You need the
> clock to be in a loop:
>
>    clock : process
>    begin
>      loop
>        clk<='0';
>        wait for 5 ns;
>        clk<='1';
>        wait for 5 ns;
>      end loop;
>    end process clock;
>
> -Dave Pollum

The clock process is Ok as is - there doesn't need to be a loop. Since
there's no 'wait' statement at the end of the process, execution will
go back to the top of the process on the next delta cycle.

This stimulus process could use some work, though. Try defining the
reset and enable signals from the beginning, like this:

   stimulus : process
   begin
      reset <= '0';
      enable <= '0';
      wait for 5 ns; reset  <= '1';
      wait for 4 ns; reset  <= '0';
      wait for 4 ns; enable <= '1';
    wait;
  end process stimulus;

Otherwise, the reset and enable signals are 'U" until you drive them
in the testbench. This could cause U's and X's to propagate through
your DUT, and the feedback in the counter could make them last
forever.

Hope this helps,

Dave

On May 14, 6:36 pm, Dave <dhsch...@gmail.com> wrote:
> On May 14, 11:47 am, Dave Pollum <vze24...@verizon.net> wrote:
>
>
>
> > On May 14, 7:09 am, Zorjak <Zor...@gmail.com> wrote:
>
> > > Hi!!!
>
> > > I started recently with the xilinx software and these days I am trying
> > > to become more familiar with the modelsim and ise. I  wanted to test
> > > some basic counter simulation in modelsim so I used this simple code
>
> > > counter design file
>
> > > library ieee ;
> > >   use ieee.std_logic_1164.all;
> > >    use ieee.std_logic_unsigned.all;
>
> > >   entity counter is
> > >    port(  clk:  in std_logic;
> > >      reset:  in std_logic;
> > >      enable:  in std_logic;
> > >      count:  out std_logic_vector(3 downto 0)
> > >   );
> > >   end counter;
>
> > >   architecture behav of counter is
> > >     signal pre_count: std_logic_vector(3 downto 0);
> > >     begin
> > >       process(clk, enable, reset)
> > >       begin
> > >         if reset = '1' then
> > >           pre_count <= "0000";
> > >        elsif (clk='1' and clk'event) then
> > >           if enable = '1' then
> > >            pre_count <= pre_count + "1";
> > >           end if;
> > >         end if;
> > >       end process;
> > >       count <= pre_count;
> > >   end behav;
>
> > > testbench
>
> > >   library ieee ;
> > >   use ieee.std_logic_1164.all;
> > >   use ieee.std_logic_unsigned.all;
> > >   use ieee.std_logic_textio.all;
> > >   use std.textio.all;
>
> > >   entity counter_tb is
> > >   end;
>
> > >   architecture counter_tb of counter_tb is
>
> > >  component counter
> > >    port ( count : out std_logic_vector(3 downto 0);
> > >           clk   : in std_logic;
> > >           enable: in std_logic;
> > >           reset : in std_logic);
> > >  end component ;
>
> > >  signal   clk    : std_logic := '0';
> > >  signal   reset  : std_logic := '0';
> > >  signal   enable : std_logic := '0';
> > >  signal   count  : std_logic_vector(3 downto 0);
>
> > >  begin
>
> > >   dut : counter
> > >  port map (
> > >      count => count,
> > >      clk   => clk,
> > >     enable=> enable,
> > >     reset => reset );
>
> > >    clock : process
> > >    begin
> > >        clk<='0';
> > >        wait for 5 ns;
> > >        clk<='1';
> > >        wait for 5 ns;
> > >    end process clock;
>
> > >    stimulus : process
> > >    begin
>
> > >      wait for 5 ns; reset  <= '1';
> > >       wait for 4 ns; reset  <= '0';
> > >       wait for 4 ns; enable <= '1';
> > >     wait;
> > >   end process stimulus;
>
> > > but my simulation doesn't give right results. (I am getting U state on
> > > all inputs). I am trying to find my mistake for more than 4 hours so
> > > please if someone could help me please do it. I have defined new
> > > project, I have compiled files and when I start simulation this
> > > results repeat over and over again. I fell that this is stupid little
> > > mistake but I can't find it no matter  what.
>
> > > Thanks for any kind of help
> > > Zoran
>
> > Your clock process will only produce -1- clock cycle.  You need the
> > clock to be in a loop:
>
> >    clock : process
> >    begin
> >      loop
> >        clk<='0';
> >        wait for 5 ns;
> >        clk<='1';
> >        wait for 5 ns;
> >      end loop;
> >    end process clock;
>
> > -Dave Pollum
>
> The clock process is Ok as is - there doesn't need to be a loop. Since
> there's no 'wait' statement at the end of the process, execution will
> go back to the top of the process on the next delta cycle.
>
> This stimulus process could use some work, though. Try defining the
> reset and enable signals from the beginning, like this:
>
>    stimulus : process
>    begin
>       reset <= '0';
>       enable <= '0';
>       wait for 5 ns; reset  <= '1';
>       wait for 4 ns; reset  <= '0';
>       wait for 4 ns; enable <= '1';
>     wait;
>   end process stimulus;
>
> Otherwise, the reset and enable signals are 'U" until you drive them
> in the testbench. This could cause U's and X's to propagate through
> your DUT, and the feedback in the counter could make them last
> forever.
>
> Hope this helps,
>
> Dave

Thanks to everybody for the help. As I said I am beginner with
modelsim so I was making mistake when I was starting my simulation.
After I was starting simulation I was choosing both files (design and
testbench) and I should chose only testbench file. So this was
problem. At the end I tried to select only testbench file and it
worked fine and there was no end of my happiness:):):)

One more time, thanks to everyone
Zoran