Stratix IV Announced

Altera have put out a press release announcing Stratix IV. Handbook
http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf.
Interestingly it's gone 40nm and does not appear to have a true 3.3V
compatability so buy your shares in manufacurers of bus switches now.

John Adair
Enterpoint Ltd.

John,

If you want some real entertainment:

http://www.pldesignline.com/showArticle.jhtml?articleID=207000972

Austin

John Adair wrote:
> Altera have put out a press release announcing Stratix IV. Handbook
> http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf.
> Interestingly it's gone 40nm and does not appear to have a true 3.3V
> compatability so buy your shares in manufacurers of bus switches now.

Only partially.
They do not state a Typical 3.3V, but they do say this

The Abs Max spec 3.75V,
V @ IO spec 3.6V


The overshoot even gives a rather strange/interesting Volts/Time
plot, where 4V overshoot is allowed 100% time, but 4.45V is
limited to 1% of the time.

What they do NOT say, is what happens if the 4.45V is there for 2% of 
the time :)

Does the device
a) Fry immediately it exceeds the 1.080% time allowance ?
(Their precision is impressve!)
b) Think about it for a while, then Fry ?
c) Suffer a gradual leakage degradation, so it exceeds
the 10uA spec, after the Volt-Time threshold.
d) If c) then can the device fail, or just drift out of
spec, and does that drift have a limit ?


Lifetime of device ? Err ?! - They give an example of 10 years,
but what should one do for a 5 year, or 20 year design life ?

There is some underlying mechanism they are trying to spec here,
but would it not make more sense, to identify that mechanism,
than use this rather silly (partial) table, that raises more
questions than it answers ?

-jg

They've also released Hardcopy-IV, including serdes and PCI-e.  Why bother
with ASICs...

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Jim

They say somewhere I saw that 3.3V operation the bank voltage is
recommended to be 3.0V so that the protection diodes work. It's
probably less of a problem the way thay have done it than what Xilinx
did in the early Spartan-3 in that it can take a 3.3V driven input.
There s not a lot of margin though if all the power supply tolerances
are taken into account.

John Adair
Enterpoint Ltd.

On 19 May, 23:11, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> John Adair wrote:
> > Altera have put out a press release announcing Stratix IV. Handbook
> >http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf.
> > Interestingly it's gone 40nm and does not appear to have a true 3.3V
> > compatability so buy your shares in manufacurers of bus switches now.
>
> Only partially.
> They do not state a Typical 3.3V, but they do say this
>
> The Abs Max spec 3.75V,
> V @ IO spec 3.6V
>
> The overshoot even gives a rather strange/interesting Volts/Time
> plot, where 4V overshoot is allowed 100% time, but 4.45V is
> limited to 1% of the time.
>
> What they do NOT say, is what happens if the 4.45V is there for 2% of
> the time :)
>
> Does the device
> a) Fry immediately it exceeds the 1.080% time allowance ?
> (Their precision is impressve!)
> b) Think about it for a while, then Fry ?
> c) Suffer a gradual leakage degradation, so it exceeds
> the 10uA spec, after the Volt-Time threshold.
> d) If c) then can the device fail, or just drift out of
> spec, and does that drift have a limit ?
>
> Lifetime of device ? Err ?! - They give an example of 10 years,
> but what should one do for a 5 year, or 20 year design life ?
>
> There is some underlying mechanism they are trying to spec here,
> but would it not make more sense, to identify that mechanism,
> than use this rather silly (partial) table, that raises more
> questions than it answers ?
>
> -jg

Joseph,

Why bother?  Only because all of the 'other' solutions actually exist,
where H4 is a hyper-active sales pitch for an untested capability that
hasn't even been taped out yet...

Imagine all those Altera customers who designed in the Stratix III GX:
all dressed up, and nowhere to go.


Using FPGAs is all about reducing risk.  Converting the FPGA to an ASIC
(structured or otherwise) is all about reducing costs.

No risk: Virtex 5, today, available

Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because
they are IDENTICAL to the FPGA

Austin

Joseph wrote:

> They've also released Hardcopy-IV, including serdes and PCI-e.
> Why bother with ASICs...

austin wrote:
> Joseph,
> Why bother?  Only because all of the 'other' solutions actually exist,

I believe Joseph said,
    "Why bother with ASICs"
not "Why bother with Xilinx"

> where H4 is a hyper-active sales pitch for an untested capability that
> hasn't even been taped out yet...

Let he who is without sin,
cast the first stone.

        -- Mike Treseler

austin wrote:
> Joseph,
> 
> Imagine all those Altera customers who designed in the Stratix III GX:
> all dressed up, and nowhere to go.

Maybe Altera also shares roadmaps like you do to bigger customers, and
those designers maybe do not exist... Imagine all those V4FX designers
who wanted working fast tranceivers.

I would say all vendors offer surprises to customers who are using
leading edge devices.

> Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because
> they are IDENTICAL to the FPGA

My opinion is that EasyPath is the worst of the two worlds. It has
limitations in flexibility, and the possibilities with price are
not that great because it is the same silicon. Better to have either
the full flexibility which costs or then the lowest possible cost
with no flexibility.

--Kim

On May 20, 10:17=A0pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
> austin wrote:
> > Joseph,
>
> > Imagine all those Altera customers who designed in the Stratix III GX:
> > all dressed up, and nowhere to go.
>
> Maybe Altera also shares roadmaps like you do to bigger customers, and
> those designers maybe do not exist... Imagine all those V4FX designers
> who wanted working fast tranceivers.
>
> I would say all vendors offer surprises to customers who are using
> leading edge devices.
>
> > Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because
> > they are IDENTICAL to the FPGA
>
> My opinion is that EasyPath is the worst of the two worlds. It has
> limitations in flexibility, and the possibilities with price are
> not that great because it is the same silicon. Better to have either
> the full flexibility which costs or then the lowest possible cost
> with no flexibility.
>
> --Kim

Let's not turn this into a marketing slugfest.
It does not take a genius to figure out why Altera was forced to
embark on such a risky gamble...
"We live in interesting times"
Peter Alfke

On May 21, 8:07=A0am, Peter Alfke <al...@sbcglobal.net> wrote:
> On May 20, 10:17=A0pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
>
>
>
>
>
> > austin wrote:
> > > Joseph,
>
> > > Imagine all those Altera customers who designed in the Stratix III GX:=

> > > all dressed up, and nowhere to go.
>
> > Maybe Altera also shares roadmaps like you do to bigger customers, and
> > those designers maybe do not exist... Imagine all those V4FX designers
> > who wanted working fast tranceivers.
>
> > I would say all vendors offer surprises to customers who are using
> > leading edge devices.
>
> > > Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because=

> > > they are IDENTICAL to the FPGA
>
> > My opinion is that EasyPath is the worst of the two worlds. It has
> > limitations in flexibility, and the possibilities with price are
> > not that great because it is the same silicon. Better to have either
> > the full flexibility which costs or then the lowest possible cost
> > with no flexibility.
>
> > --Kim
>
> Let's not turn this into a marketing slugfest.
> It does not take a genius to figure out why Altera was forced to
> embark on such a risky gamble...
> "We live in interesting times"
> Peter Alfke- Hide quoted text -
>
> - Show quoted text -

And So the fudd begings to flow :) Or should we talk about sour
grapes.