Hi All, When compiling a design I receive the following message: :Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary will appear in the map report. This summary will show a MINIMUM net delay for the paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual. For more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter. The problem however is that I receive no information WHICH SIGNAL PATH generates that problem, so I'm not able to redesign my core... The timing constraints are already the most liberal to be accepted by external hardware. How to identify the path generating the problem? I can not run the timing analyzer, because the map fails. -- TIA & regards, Wojtek Zabolotny
timing constraint is impossible to meet
Started by ●May 21, 2008
Reply by ●May 21, 20082008-05-21
"Wojciech Zabolotny" <wzab@ipebio15.ise.pw.edu.pl> wrote in message news:slrng37qjj.ab6.wzab@ipebio15.ise.pw.edu.pl...> Hi All, > > When compiling a design I receive the following message: > > :Pack:1653 - At least one timing constraint is impossible to meet because > component delays alone exceed the constraint. A physical timing > constraint > summary will appear in the map report. This summary will show a MINIMUM > net > delay for the paths. For more information about the Timing Analyzer, > consult > the Xilinx Timing Analyzer Reference manual. For more information on > TRCE, > consult the Xilinx Development System Reference Guide "TRACE" chapter. > > The problem however is that I receive no information WHICH SIGNAL PATH > generates that problem, so I'm not able to redesign my core... > The timing constraints are already the most liberal to be accepted by > external > hardware. > > How to identify the path generating the problem? > I can not run the timing analyzer, because the map fails. > -- > TIA & regards, > Wojtek ZabolotnyHi Wojtek, In the ISE GUI (I'm using 8.2 at the moment; I hope your version is similar), find the 'Processes' window. Expand the section 'Implement Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If you double-click 'Analyze Post-Map Static Timing', it'll churn away and eventually open the timing analyser. You can then find what path is failing. The key insight is to run the timing analyser on the map results, before you enter the P&R phase. HTH, Syms.
Reply by ●May 21, 20082008-05-21
> > How to identify the path generating the problem? > > I can not run the timing analyzer, because the map fails. > > -- > > TIA & regards, > > Wojtek Zabolotny > > Hi Wojtek, > In the ISE GUI (I'm using 8.2 at the moment; I hope your version is > similar), find the 'Processes' window. Expand the section 'Implement > Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If you > double-click 'Analyze Post-Map Static Timing', it'll churn away and > eventually open the timing analyser. You can then find what path is failing. > The key insight is to run the timing analyser on the map results, before you > enter the P&R phase. > HTH, Syms.The problem is, that I can not 'Generate Post-Map Static Timing', because the map fails! -- Wojtek
Reply by ●May 21, 20082008-05-21
On Wed, 21 May 2008 02:54:02 -0700 (PDT), wzab <wzab01@gmail.com> wrote:>> > How to identify the path generating the problem? >> > I can not run the timing analyzer, because the map fails. >> > -- >> > TIA & regards, >> > Wojtek Zabolotny >> >> Hi Wojtek, >> In the ISE GUI (I'm using 8.2 at the moment; I hope your version is >> similar), find the 'Processes' window. Expand the section 'Implement >> Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If you >> double-click 'Analyze Post-Map Static Timing', it'll churn away and >> eventually open the timing analyser. You can then find what path is failing. >> The key insight is to run the timing analyser on the map results, before you >> enter the P&R phase. >> HTH, Syms. > >The problem is, that I can not 'Generate Post-Map Static Timing', >because the map fails!Relax the timing until it maps, then you can find the slowest paths (at PAR if necessary). Fix these and retry. Then tighten the timings a bit. Repeat until done. It's frustrating, I agree. Map should have completed, just to let you run the report. Alternatively, what did synthesis report as the longest paths? Did they exceed your timing constraints? It may be worth fixing those first. (However, synthesis may not see the longest path if you are using black box components) - Brian
Reply by ●May 21, 20082008-05-21
"wzab" <wzab01@gmail.com> wrote in message news:7572b54b-1e31-433c-8c08-cd96f69d8351@k37g2000hsf.googlegroups.com...>> > How to identify the path generating the problem? >> > I can not run the timing analyzer, because the map fails. >> > -- >> > TIA & regards, >> > Wojtek Zabolotny >> >> Hi Wojtek, >> In the ISE GUI (I'm using 8.2 at the moment; I hope your version is >> similar), find the 'Processes' window. Expand the section 'Implement >> Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If >> you >> double-click 'Analyze Post-Map Static Timing', it'll churn away and >> eventually open the timing analyser. You can then find what path is >> failing. >> The key insight is to run the timing analyser on the map results, before >> you >> enter the P&R phase. >> HTH, Syms. > > The problem is, that I can not 'Generate Post-Map Static Timing', > because the map fails! > -- > WojtekOK, soz that didn't help you, ISE 8.2 doesn't seem to behave like that, I've only experienced this problem when it does the timing stuff in P&R. Out of interest, what version of the tools are you using? It sounds like a big backwards step from what I'm used to! Maybe there's a switch to turn off timing driven mapping? Cheers, Syms. p.s. What Brian posted! :-)
Reply by ●May 22, 20082008-05-22
On May 21, 2:54=A0pm, wzab <wza...@gmail.com> wrote:> > > How to identify the path generating the problem? > > > I can not run the timing analyzer, because the map fails. > > > -- > > > TIA & regards, > > > Wojtek Zabolotny > > > Hi Wojtek, > > In the ISE GUI (I'm using 8.2 at the moment; I hope your version is > > similar), find the 'Processes' window. Expand the section 'Implement > > Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If y=ou> > double-click 'Analyze Post-Map Static Timing', it'll churn away and > > eventually open the timing analyser. You can then find what path is fail=ing.> > The key insight is to run the timing analyser on the map results, before=you> > enter the P&R phase. > > HTH, Syms. > > The problem is, that I can not 'Generate Post-Map Static Timing', > because the map fails! > -- > WojtekHere one point is not clear to me. How a timing constraint forces the map to fail.If every thing (in the design) is correct then it passes the map with timing errors.I think there is some problem in the design which is forcing the map to fail.
Reply by ●May 22, 20082008-05-22
Brian Drummond wrote:> On Wed, 21 May 2008 02:54:02 -0700 (PDT), wzab <wzab01@gmail.com> wrote: > >>>> How to identify the path generating the problem? >>>> I can not run the timing analyzer, because the map fails. >>>> -- >>>> TIA & regards, >>>> Wojtek Zabolotny >>> double-click 'Analyze Post-Map Static Timing', it'll churn away and >>> eventually open the timing analyser. You can then find what path is failing. >>> The key insight is to run the timing analyser on the map results, before you >>> enter the P&R phase. >>> HTH, Syms. >> The problem is, that I can not 'Generate Post-Map Static Timing', >> because the map fails! > > Relax the timing until it maps, then you can find the slowest paths (at > PAR if necessary). Fix these and retry. Then tighten the timings a bit. > Repeat until done.I've seen a similar issue, but it wasn't related to clock period constraints. The offset in constraint was applied to input pins that had some combinatorial logic before getting latched by a flop. The offset in wasn't too tight by itself, but the extra combinatorial cloud was making it impossible to meet, hence a similar error. Start looking at offset in/out constraints, since it sounds like your clock constraints are relaxed enough. HTH, -P@
Reply by ●May 22, 20082008-05-22
"wzab" <wzab01@gmail.com> wrote in message news:7572b54b-1e31-433c-8c08-cd96f69d8351@k37g2000hsf.googlegroups.com...>> > How to identify the path generating the problem? >> > I can not run the timing analyzer, because the map fails. >> > -- >> > TIA & regards, >> > Wojtek Zabolotny >> >> Hi Wojtek, >> In the ISE GUI (I'm using 8.2 at the moment; I hope your version is >> similar), find the 'Processes' window. Expand the section 'Implement >> Design', then expand 'Map', then 'Generate Post-Map Static Timing'. If >> you >> double-click 'Analyze Post-Map Static Timing', it'll churn away and >> eventually open the timing analyser. You can then find what path is >> failing. >> The key insight is to run the timing analyser on the map results, before >> you >> enter the P&R phase. >> HTH, Syms. > > The problem is, that I can not 'Generate Post-Map Static Timing', > because the map fails! > -- > WojtekTry this environmental variable before running P&R set XIL_TIMING_ALLOW_IMPOSSIBLE=1 Hans www.ht-lab.com
Reply by ●May 22, 20082008-05-22
HT-Lab wrote:> Try this environmental variable before running P&R > > set XIL_TIMING_ALLOW_IMPOSSIBLE=1 > > Hans > www.ht-lab.com > >Can I mention the deep and abiding love I have for whoever decided that the options to MAP needed to be passed through a combination of command line arguments, settings files, and nearly undocumented environment variables, with any given setting only accessible through one of those? That hasn't complicated my build chain one tiny bit, nosireebob. -- Rob Gaddi, Highland Technology Email address is currently out of order
Reply by ●May 22, 20082008-05-22
On Thu, 22 May 2008 08:12:14 +0100, "HT-Lab" wrote:>set XIL_TIMING_ALLOW_IMPOSSIBLE=1Hey, that's not fair... When I want to do a "never ifdef" by testing an env var or macro that is sure to be absent, I usually use IMPOSSIBLE_THINGS_BEFORE_BREAKFAST - and that one is getting awfully, awfully close :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
