asic gate count

Hi,
I am looking for some tool / ip that can give me approximate gate
count of mapper/demapper. Any helpful hint is greatly welcome.

Thanks,
Vijayant

<vijayant.rutgers@gmail.com> wrote in message 
news:57662a9c-7a37-4470-9468-faf94a5422f7@8g2000hse.googlegroups.com...
> Hi,
> I am looking for some tool / ip that can give me approximate gate
> count of mapper/demapper. Any helpful hint is greatly welcome.
>
> Thanks,
> Vijayant


To get a gate count ... you have to synthesize it, the synthesis will give 
you an area and typical a "gate" is a 2 input NAND gate. So divide you're 
total area by the area of the NAND gate and that is your gate count.

Mike 

vijayant.rutgers@gmail.com wrote:

> I am looking for some tool / ip that can give me approximate gate
> count of mapper/demapper. Any helpful hint is greatly welcome.

The traditional method for ASIC is to divide the number
of transistors by the number of transistors in a 2 input
NAND gate.  For CMOS, that is four.

Good or bad, that is the usual way.

-- glen

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:hvydnRGK27J_zKvVnZ2dnUVZ_uqdnZ2d@comcast.com...
> vijayant.rutgers@gmail.com wrote:
>
>> I am looking for some tool / ip that can give me approximate gate
>> count of mapper/demapper. Any helpful hint is greatly welcome.
>
> The traditional method for ASIC is to divide the number
> of transistors by the number of transistors in a 2 input
> NAND gate.  For CMOS, that is four.
>
> Good or bad, that is the usual way.
>
> -- glen
>

What is your method for determining how many transistors are in the design? 
My synthesis tools only give me area.

Mike 

> What is your method for determining how many transistors are in the design?
> My synthesis tools only give me area.

Divide the area of your design by the area of a 2-input NAND with
lowest drive strength * 4.

Cheers,
Jon

Mike Lewis wrote:
(snip)

>>The traditional method for ASIC is to divide the number
>>of transistors by the number of transistors in a 2 input
>>NAND gate.  For CMOS, that is four.
(snip)

> What is your method for determining how many transistors are in the design? 
> My synthesis tools only give me area.

Last I knew, they gave transistors, but that was some time ago.

For FPGA it is much harder to give a reliable count, and
you are asking in an FPGA newsgroup.

If it gives gate counts different types of gates and with a
little guessing on transistors/gate.   Is this for standard
cell, sea of gates, or something else?  I thought I used to
have pretty detailed information on the standard cell libraries,
including transistors for each library element.

-- glen

I have a design on FPGA that is ready. However, we need to have some
mapping from fpga design to asic. I know that this will not be
accurate. But accuracy is not our concern right now. We just need
upper bound.  Also, we are also looking for some IP Core for ASIC so
that we can rough estimate.

Regards,
Vijayant



On May 24, 5:47=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Mike Lewis wrote:
>
> (snip)
>
> >>The traditional method for ASIC is to divide the number
> >>of transistors by the number of transistors in a 2 input
> >>NAND gate. =A0For CMOS, that is four.
>
> (snip)
>
> > What is your method for determining how many transistors are in the desi=
gn?
> > My synthesis tools only give me area.
>
> Last I knew, they gave transistors, but that was some time ago.
>
> For FPGA it is much harder to give a reliable count, and
> you are asking in an FPGA newsgroup.
>
> If it gives gate counts different types of gates and with a
> little guessing on transistors/gate. =A0 Is this for standard
> cell, sea of gates, or something else? =A0I thought I used to
> have pretty detailed information on the standard cell libraries,
> including transistors for each library element.
>
> -- glen

On 28 Mai, 20:24, <vijayant.rutg...@gmail.com> wrote:
> I have a design on FPGA that is ready. However, we need to have some
> mapping from fpga design to asic. I know that this will not be
> accurate. But accuracy is not our concern right now. We just need
> upper bound.  Also, we are also looking for some IP Core for ASIC so
> that we can rough estimate.

Take the nuber of registers and combinatorial cells used for the fpga.
Start with the registers, inspect if you have register doubling in
synthesis for load balance and ask yourself if you need this register
doubling. In ASIC you have often load balancing with buffering.
For combinatorical logic you should have a look, what type of cells is
in your vendors library.
For a lot of technologies the tool will more likely use 3 input cells
instead of 4 input cells. This will roughly increase your
combinatorical cell count by 10%-30% (it depends on the design).
You should take into account, that you need to add something like 10%
buffering for global nets and timing correction that comes for free in
an fpga.

bye Thomas

On Wed, 28 May 2008 11:24:03 -0700 (PDT), "vijayant.rutgers@gmail.com"
<vijayant.rutgers@gmail.com> wrote:

>I have a design on FPGA that is ready. However, we need to have some
>mapping from fpga design to asic. I know that this will not be
>accurate. But accuracy is not our concern right now. We just need
>upper bound.  Also, we are also looking for some IP Core for ASIC so
>that we can rough estimate.
>
>Regards,
>Vijayant
>
One approach is to run it through the Xilinx tools and review the map
report (.mrp file). If you take this approach, I suggest eliminating
memory blocks (PPC if used) and DSP/multiplier blocks and re-running, to
understand how much of the gate count comes from these blocks.

- Brian

Hi Vijayant,
every "rule of thumb" you are trying to use will give you a misleading 
result. Even if you just want a maximum value.

The only way to get a nearly accurate number is to synthesize your 
design with an asic synthesis tool using the desired technology library.

You may use a default synthesis at first, to get an idea of the size and 
gate count. These results may vary depending on your design goals. If 
you want to increase speed your design may become larger. If speed is 
negotiable the design may become smaller with some area optimization 
constraints.

However, the result of this synthesis will be an area value (most likely 
in square micro meters) because the used gates (and flipflops) heavily 
vary in size and transistor count. Unless you are using a sea of gates 
technology that has only nand2-elements.

To give you an idea think about this:

If you have a simple 4to1 mux, this may be synthesized with a single 
mux4 cell in some standard cell technologies. With a sea of gates 
technology you need a bunch of nand2's for this function, plus some 
routing resources.
So, how would you express the number of gates in these two cases?
The mux4 is just the solution with the minimum number of cells. 
depending on your constraints the result might be any correct 
combination of simpler gates.

Also, the gate count, however calculated is not relevant for production.
Only the area tells you how many chips can be fabricated on a single 
waver. And the area changes with the used technology of course.
So 1000 gates in a 130nm technology yield less chips per waver than 2000 
gates in a 45nm technology. (rough estimation, just to give you an idea)

So forget gate counts if you want to compare technologies.
Only use of gate counts is if you want to compare designs using the same 
technology. And I mean the very same technology! (Just take a look at 
some of the fruitless gate count discussions about Brand-A and Brand-X 
FPGAs)

Have a nice synthesis
   Eilert


vijayant.rutgers@gmail.com schrieb:
> I have a design on FPGA that is ready. However, we need to have some
> mapping from fpga design to asic. I know that this will not be
> accurate. But accuracy is not our concern right now. We just need
> upper bound.  Also, we are also looking for some IP Core for ASIC so
> that we can rough estimate.
> 
> Regards,
> Vijayant
> 
> 
> 
> On May 24, 5:47 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>> Mike Lewis wrote:
>>
>> (snip)
>>
>>>> The traditional method for ASIC is to divide the number
>>>> of transistors by the number of transistors in a 2 input
>>>> NAND gate.  For CMOS, that is four.
>> (snip)
>>
>>> What is your method for determining how many transistors are in the design?
>>> My synthesis tools only give me area.
>> Last I knew, they gave transistors, but that was some time ago.
>>
>> For FPGA it is much harder to give a reliable count, and
>> you are asking in an FPGA newsgroup.
>>
>> If it gives gate counts different types of gates and with a
>> little guessing on transistors/gate.   Is this for standard
>> cell, sea of gates, or something else?  I thought I used to
>> have pretty detailed information on the standard cell libraries,
>> including transistors for each library element.
>>
>> -- glen
>