Xilinx Clock Doubler

I have a 10MHz clock but needed a 20MHz clock speed.  I used two
asynchronous clear flip flops with a series of buffers to add delay to
the signal.

Is this a bad practice?  Will it fail with time or temperature?  It
works fine on a PCB, but I am concerned!  It does exactly what I want,
increment the counter on both rising and falling edges.

http://www.stockly.com/images4/080529-Clock_Doubler.jpg

Above is a link to a picture the Xilinx schematic.

Thanks

Grant

If this is NOT recommended, then would 2 two bit counters (one with an
inverted clock) and a 4 bit adder be the best solution?  I'd like to
keep my clock at 10MHz.

"Grant Stockly" <grant@stockly.com> wrote in message 
news:f7276c42-5e33-4b6e-96e1-d16afeae08cb@p25g2000pri.googlegroups.com...
> If this is NOT recommended, then would 2 two bit counters (one with an
> inverted clock) and a 4 bit adder be the best solution?

That's almost certainly not the 'best' solution. A better solution is to use 
a DCM to double the frequency. At 10MHz input frequency, you'll need to use 
its CLKFX output.

> I'd like to keep my clock at 10MHz.

No you wouldn't. You'd like to keep your logic clock _enabled_ at 10MHz, but 
clocked by your newly DCMed 20MHz clock.

HTH., Syms.

p.s. Designing with schematics? How quaint! ;-) 

On May 29, 1:23=A0am, Grant Stockly <gr...@stockly.com> wrote:
> I have a 10MHz clock but needed a 20MHz clock speed. =A0I used two
> asynchronous clear flip flops with a series of buffers to add delay to
> the signal.
>
> Is this a bad practice? =A0Will it fail with time or temperature? =A0It
> works fine on a PCB, but I am concerned! =A0It does exactly what I want,
> increment the counter on both rising and falling edges.
>
> http://www.stockly.com/images4/080529-Clock_Doubler.jpg
>
> Above is a link to a picture the Xilinx schematic.
>
> Thanks
>
> Grant

Grant, years ago I published a reliable clock doubler circuit, part of
the "six easy pieces" that seem to be lost.
In words:
Run your 10 MHz clock through a 2-input XOR.
Generate a toggling flip-flop by feeding Q back through an inverting
LUT to the D input.
Route the signal driving D also to the second XOR input.
Use the XOR output to clock the flip-flop, and also use it as your 20
MHz clock.

Disadvantage: If your 10 MHz doesn't have 50/50 duty cycle, your 20
MHz will have frequency modulation.
And the High (or Low depending on XOR or XNOR) time of your 20 MHz
clock will be short but you can lengthen it by adding delay to the Q-
to-D path. Anyhow, it's self-adaptive to the device speed. Use this
trick only when no PLL or DLL is available.
Peter Alfke

Peter Alfke wrote:
> Grant, years ago I published a reliable clock doubler circuit, part of
> the "six easy pieces" that seem to be lost.

I repeat my request that the Xilinx marketing and/or web people put all
the old stuff that they unceremoniously removed back into an archive
section of the web or FTP site.

The "six easy pieces" article is exactly the sort of thing that I was
worried would be lost.  :-(

Just because application notes and white papers are old does NOT mean
that they aren't of any use to Xilinx customers.

Eric

> > If this is NOT recommended, then would 2 two bit counters (one with an
> > inverted clock) and a 4 bit adder be the best solution?
>
> That's almost certainly not the 'best' solution. A better solution is to use
> a DCM to double the frequency. At 10MHz input frequency, you'll need to use
> its CLKFX output.
>
> > I'd like to keep my clock at 10MHz.
>
> No you wouldn't. You'd like to keep your logic clock _enabled_ at 10MHz, but
> clocked by your newly DCMed 20MHz clock.
>
> HTH., Syms.
>
> p.s. Designing with schematics? How quaint! ;-)

I will learn Verilog or VHDL soon!  : )  I promise!

I spent a few months pouring over the Homebrewcpu.com schematics and
now find it easy to visualize what I want to do.  : )

"Grant Stockly" <grant@stockly.com> wrote in message 
news:9e47c9b5-5269-46ac-b640-1d85a53da66b@y22g2000prd.googlegroups.com...
>> p.s. Designing with schematics? How quaint! ;-)
>
> I will learn Verilog or VHDL soon!  : )  I promise!
>
> I spent a few months pouring over the Homebrewcpu.com schematics and
> now find it easy to visualize what I want to do.  : )

Hi Grant,
:-)
I tell you what, if more people adopted your learning approach, there would 
be fewer folks on comp.arch.fpga struggling to understand why their 'System 
C' code works in ModelSIM but doesn't work in their Spartan2e. Simulation 
aside, HDLs are merely great shortcuts for implementing the hardware that 
the designer has visualised. For sure, I still 'see' schematics in my head 
when I write my VHDL.

Going back to your original post, I'd recommend to anyone starting out 
designing FPGAs to do more reading about FPGA clocking. If you can meet the 
timing, the rest is junior engineering!

Cheers, Syms. 

On May 29, 8:58 am, Peter Alfke <pe...@xilinx.com> wrote:
> On May 29, 1:23 am, Grant Stockly <gr...@stockly.com> wrote:
>
> > I have a 10MHz clock but needed a 20MHz clock speed.  I used two
> > asynchronous clear flip flops with a series of buffers to add delay to
> > the signal.
>
> > Is this a bad practice?  Will it fail with time or temperature?  It
> > works fine on a PCB, but I am concerned!  It does exactly what I want,
> > increment the counter on both rising and falling edges.
>
> >http://www.stockly.com/images4/080529-Clock_Doubler.jpg
>
> > Above is a link to a picture the Xilinx schematic.
>
> > Thanks
>
> > Grant
>
> Grant, years ago I published a reliable clock doubler circuit, part of
> the "six easy pieces" that seem to be lost.
> In words:
> Run your 10 MHz clock through a 2-input XOR.
> Generate a toggling flip-flop by feeding Q back through an inverting
> LUT to the D input.
> Route the signal driving D also to the second XOR input.
> Use the XOR output to clock the flip-flop, and also use it as your 20
> MHz clock.
>
> Disadvantage: If your 10 MHz doesn't have 50/50 duty cycle, your 20
> MHz will have frequency modulation.
> And the High (or Low depending on XOR or XNOR) time of your 20 MHz
> clock will be short but you can lengthen it by adding delay to the Q-
> to-D path. Anyhow, it's self-adaptive to the device speed. Use this
> trick only when no PLL or DLL is available.
> Peter Alfke

I found something...

http://www.pldworld.com/_xilinx/html/tip/sixeasypieces.htm

Firefox doesn't know what to do with an htm file, Internet Explorer
wants to install language packs for the English document...but will at
least show it to you in English!  :)

Save it before its gone!  :)

Grant

"Eric Smith" <eric@brouhaha.com> wrote in message 
news:m3d4n5aqp0.fsf@donnybrook.brouhaha.com...
> Peter Alfke wrote:
>> Grant, years ago I published a reliable clock doubler circuit, part of
>> the "six easy pieces" that seem to be lost.
>
> I repeat my request that the Xilinx marketing and/or web people put all
> the old stuff that they unceremoniously removed back into an archive
> section of the web or FTP site.
>
> The "six easy pieces" article is exactly the sort of thing that I was
> worried would be lost.  :-(
>
> Just because application notes and white papers are old does NOT mean
> that they aren't of any use to Xilinx customers.
>
> Eric

Hey Eric,

Yeah, yeah, yeah. Sod that.

We're still waiting for the FPGA 'Six Not So Easy Pieces'.

Syms. :-) 

"Grant Stockly" <grant@stockly.com> wrote in message 
news:0370016c-1f93-4cb5-ba0a-3ce58b804b3f@q27g2000prf.googlegroups.com...
>
> I found something...
>
> http://www.pldworld.com/_xilinx/html/tip/sixeasypieces.htm
>
No pictures for me. :-(