ModelSim, Virtex DCM, and clk0 phase problem

Has anyone experienced the clk0 being 180 deg out of phase with the
DCM input clock during simulation (wave view) in ModelSim? I have clk0
going to clkfb through a bufg, just like what is described in the V-II
Platform Handbook (jellybean simple implementation), but after lock,
clk0 is 180 out of phase, so I do not get the wave that is shown in
the modelsim wave view in the Handbook.

My fix is to run clk180 to clkfb. Then clk0 is in phase with clkin.
But this makes no sense to me. I have not implemented on chip to see
what really happens.

As an aside, my input clock is 27MHz, but I need 13.5 MHz for my logic
with various phase relationships. Any advice? What are the
implications of running various phased 27MHz clocks into flops to get
various phased 13.5 MHz clocks?

Thanks. I am new to all this, but have to say the DCM/simulation bit
has been infinitely frustrating.

Danny

Dan,

    Sounds like you might have run into this problem:

Answer Record # 16847 5.2isp1 Simulation - DCM outputs are 180 degrees 
out of phase (UniSim and SimPrim VHDL models) 
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=16847

Generally it is a good idea to search the Xilinx Support Site when you 
encounter issues such as these as if it has been perviously identified, 
it is generally documented there.

--  Brian



Dan Braunstein wrote:

> Has anyone experienced the clk0 being 180 deg out of phase with the
> DCM input clock during simulation (wave view) in ModelSim? I have clk0
> going to clkfb through a bufg, just like what is described in the V-II
> Platform Handbook (jellybean simple implementation), but after lock,
> clk0 is 180 out of phase, so I do not get the wave that is shown in
> the modelsim wave view in the Handbook.
> 
> My fix is to run clk180 to clkfb. Then clk0 is in phase with clkin.
> But this makes no sense to me. I have not implemented on chip to see
> what really happens.
> 
> As an aside, my input clock is 27MHz, but I need 13.5 MHz for my logic
> with various phase relationships. Any advice? What are the
> implications of running various phased 27MHz clocks into flops to get
> various phased 13.5 MHz clocks?
> 
> Thanks. I am new to all this, but have to say the DCM/simulation bit
> has been infinitely frustrating.
> 
> Danny