Sorry about the title, everyone put down the flamethrowers, lol. I have a few questions about Xilinx and Altera (actually Spartan-3E versus Cyclone III) which relate to a particular project, so here are the specifics. Currently the prototype system is on a Spartan-3E 500 to validate the design, and it works. This was for development, though, as for the final version a larger FPGA is needed ; the 500E is starting to feel a bit tight. This FPGA system has : - Microblaze with caches (small caches) - 16 bit SDRAM with mch_opb_sdram controller (without OPB actually) - CPU connected to RAM through the MCH/XCL - Ethernet LAN9117 MAC+PHY, with DMA to SDRAM via MCH/XCL - IO peripheral, with DMA to SDRAM via MCH/XCL - And lots of IOs (well not so many on PQ208 but final version will have a larger FPGA). Here is what it does : - Receives data from PC over ethernet in UDP packets - Buffer in SDRAM - Output data in user's format of choice on the pins - Read data from pins - Buffer - Send back to PC in UDP packets A simple protocol (not finished) will handle UDP retransmissions etc a-la-TCP but with very low latency. Primary purpose is to transfer multichannel audio (up to about 8-9 megabytes/s) but also digital scope (sample, buffer, send to PC) and other data acquisition applications. It will also need to do some DSP work on the audio (resampling, dithering, and some complicated filtering, etc) and possibly DSP on the acquired signals in a DAQ scenario. Now. Three problems. Everything is good with Xilinx except the DSP part, I guess the logic would fit in a Spartan-E3 1200 with lots of room to spare except I might be short on multipliers. Now that would be a problem to realize that once the final board is made ! So I thought about Spartan-3A DSP but it has a packaging problem : 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. Second problem, this SDRAM is really crummy and so is mch_opb_sdram. Granted, I get 90 MB/s from a 16 bit SDRAM running at 50 MHz which is good. But it runs at 50 MHz !!! I should have put some DDR. So the second requirement is an easy interface to a 16 bit DDR chip with a FREE core that supports some good fast DMA like the mch_opb does. I really like this way of accessing memory, the CPU doesn't even have to touch it, my data IO core self-serves from memory, I like that. Ethernet is slow (20 MB/s) but as I said I want to use it also for some data acquisition which means writing lots of data very fast to the SDRAM, since the sample rate of the converters will depend on the memory bandwidth ! Third problem, most of my IO is 3.3V but I would like to use LVDS for some signals. There are only 4 IO banks... Cyclone III (like EP3C40) on the other hand is cheap, has looots of DSP power, the FPGA itself is faster than the Spartan 3, and it has 8 banks which means I can dedicate 1/8 of the pins to LVDS and still have enough for my 3.3V IO. In other words it looks nice but I don't know anything about Altera. I loaded up the free tools and played with them a bit without much success... NIOS vs Microblaze ? I don't care, CPU utilization is far from 100% anyway, so as long as it runs and has JTAG debug I'm happy. I would like to avoid having to purchase cores, also. EDK which I got on CD with a dev kit comes with a nice assortment of memory controllers... I'm having problems decrypting the Altera licensing stuff, like what is free, and what is not... Also this board will be used as part of an open source project. We'll make a board fab run and sell them so people can hack them. I would really prefer if those guys could use free (as in beer) software and EDK is a problem there. But, so is the small collection of free Altera cores... So, from my project description above, what could I do ?...
Xilinx vs Altera
Started by ●June 4, 2008
Reply by ●June 4, 20082008-06-04
PFC wrote:> So I thought about Spartan-3A DSP but it has a packaging problem : > 0.8mm BGA ! No way. 1mm is fine but not 0.8mm.What's the big deal? I'm no expert, but is 0.8mm that much more difficult to deal with than 1.0?> Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them.Interesting. Are you planning to sell blank boards or stuffed ones? Will the PCB database be open source, or just gerber files? What particular audio applications do you think people would use it for?> I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?...What would your board bring to the table not available from the jillion of dev boards out there? multichannel audio I'm guessing. What if you made an interface board with a lot of audio on it and made it where it could connect to umpteen different boards already available. Then you could quickly adapt your IP designs to new generation devices next year and the year after. -Jeff
Reply by ●June 4, 20082008-06-04
PFC wrote: <snip>> Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?...Lattice have an open source, 32 bit processor core. Add that to your short list ? - this sounds fairly core-agnostic, so you could start with a Xilinx/Altera core, then move to lattice as the system is proven, and ready for wider deployment. -jg
Reply by ●June 4, 20082008-06-04
"PFC" <lists@peufeu.com> wrote in message news:op.ub8qcrlocigqcu@apollo13.peufeu.com...> > I have a few questions about Xilinx and Altera (actually Spartan-3E > versus Cyclone III) which relate to a particular project, so here are the > specifics. ><snip>> Also this board will be used as part of an open source project. We'll > make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) software > and EDK is a problem there. But, so is the small collection of free Altera > cores... > > So, from my project description above, what could I do ?... >1. Benchmark both with something resembling the final design. You should have all the logic connected to at least drive all of the external output/inout pins and use all of the input to at least do 'something'. For the IP that you'll be developing you'll need to generate it in a vendor neutral way, which can usually be done (except for non-inferrable things like PLL/DLLs). Try out the vendor specific cores for things you're missing even if they won't necessarily be in the final design. 1a. Try not to get too wrapped around the axle about having everything functional before moving on. There is a bit of a risk but as long nothing is getting totally optomized away, you should be able to make a reasonable benchmark. 2. Run the designs through place and route. Pay attention to the reports about unneeded I/O, make sure nothing gets optomized away, make sure that IP blocks are consuming resources (an unconnected input or output in an internal block can make the whole thing disappear). 3. Decide on what metrics are important for your project (i.e. device cost, clock speed, packaging, bigger parts in the same package, tool hassles, etc.) and evaluate all the FPGA vendors based on those metrics...also may not necessarily want to exclude the 'other guys' beside brand A and X. They're the two biggest, not the only ones. Kevin Jennings
Reply by ●June 4, 20082008-06-04
>> So I thought about Spartan-3A DSP but it has a packaging problem : >> 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. > > What's the big deal? I'm no expert, but is 0.8mm that much more > difficult to deal with than 1.0?It adds a lot to board cost. This is a hobby project, lol.>> Also this board will be used as part of an open source project. >> We'll make a board fab run and sell them so people can hack them. > > Interesting. Are you planning to sell blank boards or stuffed ones? Will > the PCB database be open source, or just gerber files? What particular > audio applications do you think people would use it for?Stuffed, I doubt people would want to solder the BGA... Open source, And multichannel remote audio soundcard with DSP capabilities. One of the guys is more interested in recording capabilities and I'm more interested in playback, anyway the hardware is the same, only difference is the number of ADC/DACs in the daughterboard... But since it's an FPGA and the audio stuff will be on a separate (much cheaper to manufacture) board it could be pretty much anything else... The "remote" part will be either ethernet (currently prototyped) or FireWire with a DICE chip (this is under review). It is not very fixed at the moment. But since Ethernet adds little cost and can serve many purposes it is here to stay.> What would your board bring to the table not available from the jillion > of dev boards out there?Low noise/EMI, small, cheap, and ethernet that works without headaches. Believe it or not I found no such thing on the market.> Lattice have an open source, 32 bit processor core. > Add that to your short list ? - this sounds fairly core-agnostic, > so you could start with a Xilinx/Altera core, then move to lattice > as the system is proven, and ready for wider deployment.Chips are hard to obtain for a hobby project. DigiKey et al only stock X & A...
Reply by ●June 4, 20082008-06-04
PFC wrote:>> Lattice have an open source, 32 bit processor core. >> Add that to your short list ? - this sounds fairly core-agnostic, >> so you could start with a Xilinx/Altera core, then move to lattice >> as the system is proven, and ready for wider deployment. > > > Chips are hard to obtain for a hobby project. DigiKey et al only > stock X & A...I was talking about the core, not the silicon. http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm If this is an open-source project, it makes sense to use an open source core ? Also, Lattice Silicon is available from Mouser, and Jameco et al. -jg
Reply by ●June 4, 20082008-06-04
>
> What's the big deal? I'm no expert, but is 0.8mm that much more
difficult to deal with than 1.0?
It adds a lot to board cost. This is a hobby project, lol.
I just did an ARM chip that had .65mm ball pitch. There aren't a lot of
guys that can laser drill and do a 3/3 technology. Yes, you pay, but get
used to it--things are getting smaller!!
PFC wrote:
>>> So I thought about Spartan-3A DSP but it has a packaging problem
>>> : 0.8mm BGA ! No way. 1mm is fine but not 0.8mm.
>>
>> What's the big deal? I'm no expert, but is 0.8mm that much more
>> difficult to deal with than 1.0?
>
> It adds a lot to board cost. This is a hobby project, lol.
>
>>> Also this board will be used as part of an open source project.
>>> We'll make a board fab run and sell them so people can hack them.
>>
>> Interesting. Are you planning to sell blank boards or stuffed ones?
>> Will the PCB database be open source, or just gerber files? What
>> particular audio applications do you think people would use it for?
>
> Stuffed, I doubt people would want to solder the BGA...
> Open source,
> And multichannel remote audio soundcard with DSP capabilities.
> One of the guys is more interested in recording capabilities and I'm
> more interested in playback, anyway the hardware is the same, only
> difference is the number of ADC/DACs in the daughterboard...
>
> But since it's an FPGA and the audio stuff will be on a separate
> (much cheaper to manufacture) board it could be pretty much anything
> else...
> The "remote" part will be either ethernet (currently prototyped) or
> FireWire with a DICE chip (this is under review). It is not very fixed
> at the moment. But since Ethernet adds little cost and can serve many
> purposes it is here to stay.
>
>> What would your board bring to the table not available from the
>> jillion of dev boards out there?
>
> Low noise/EMI, small, cheap, and ethernet that works without
> headaches. Believe it or not I found no such thing on the market.
>
>> Lattice have an open source, 32 bit processor core.
>> Add that to your short list ? - this sounds fairly core-agnostic,
>> so you could start with a Xilinx/Altera core, then move to lattice
>> as the system is proven, and ready for wider deployment.
>
> Chips are hard to obtain for a hobby project. DigiKey et al only
> stock X & A...
Reply by ●June 5, 20082008-06-05
PFC wrote:> > Sorry about the title, everyone put down the flamethrowers, lol. > > I have a few questions about Xilinx and Altera (actually Spartan-3E > versus Cyclone III) which relate to a particular project, so here are > the specifics. > Currently the prototype system is on a Spartan-3E 500 to validate > the design, and it works. This was for development, though, as for the > final version a larger FPGA is needed ; the 500E is starting to feel a > bit tight. > > This FPGA system has : > > - Microblaze with caches (small caches) > - 16 bit SDRAM with mch_opb_sdram controller (without OPB actually) > - CPU connected to RAM through the MCH/XCL > - Ethernet LAN9117 MAC+PHY, with DMA to SDRAM via MCH/XCL > - IO peripheral, with DMA to SDRAM via MCH/XCL > - And lots of IOs (well not so many on PQ208 but final version will > have a larger FPGA). > > Here is what it does : > > - Receives data from PC over ethernet in UDP packets > - Buffer in SDRAM > - Output data in user's format of choice on the pins > - Read data from pins > - Buffer > - Send back to PC in UDP packets > > A simple protocol (not finished) will handle UDP retransmissions etc > a-la-TCP but with very low latency. > > Primary purpose is to transfer multichannel audio (up to about 8-9 > megabytes/s) but also digital scope (sample, buffer, send to PC) and > other data acquisition applications. > It will also need to do some DSP work on the audio (resampling, > dithering, and some complicated filtering, etc) and possibly DSP on the > acquired signals in a DAQ scenario. > > Now. Three problems. > > Everything is good with Xilinx except the DSP part, I guess the > logic would fit in a Spartan-E3 1200 with lots of room to spare except I > might be short on multipliers. Now that would be a problem to realize > that once the final board is made ! > > So I thought about Spartan-3A DSP but it has a packaging problem : > 0.8mm BGA ! No way. 1mm is fine but not 0.8mm. > > Second problem, this SDRAM is really crummy and so is mch_opb_sdram. > Granted, I get 90 MB/s from a 16 bit SDRAM running at 50 MHz which is > good. But it runs at 50 MHz !!! I should have put some DDR. > So the second requirement is an easy interface to a 16 bit DDR chip > with a FREE core that supports some good fast DMA like the mch_opb does. > I really like this way of accessing memory, the CPU doesn't even have to > touch it, my data IO core self-serves from memory, I like that. Ethernet > is slow (20 MB/s) but as I said I want to use it also for some data > acquisition which means writing lots of data very fast to the SDRAM, > since the sample rate of the converters will depend on the memory > bandwidth ! > > Third problem, most of my IO is 3.3V but I would like to use LVDS > for some signals. There are only 4 IO banks... > > Cyclone III (like EP3C40) on the other hand is cheap, has looots of > DSP power, the FPGA itself is faster than the Spartan 3, and it has 8 > banks which means I can dedicate 1/8 of the pins to LVDS and still have > enough for my 3.3V IO. > In other words it looks nice but I don't know anything about Altera. > I loaded up the free tools and played with them a bit without much > success... > > NIOS vs Microblaze ? I don't care, CPU utilization is far from 100% > anyway, so as long as it runs and has JTAG debug I'm happy. > I would like to avoid having to purchase cores, also. EDK which I > got on CD with a dev kit comes with a nice assortment of memory > controllers... I'm having problems decrypting the Altera licensing > stuff, like what is free, and what is not... > > Also this board will be used as part of an open source project. > We'll make a board fab run and sell them so people can hack them. > I would really prefer if those guys could use free (as in beer) > software and EDK is a problem there. But, so is the small collection of > free Altera cores... > > So, from my project description above, what could I do ?... >I am not an expert on Altera licensing, but as far as I can tell you use Quartus web edition and open core evaluation during development. This means you can use the DDR core (the sdram core is always free from Altera, and runs a lot more than 50 MHz, as is their dma core) and the NIOS core while connected to Quartus with by jtag. For stand-alone use, you have to buy a NIOS license and a DDR core license (in practice, you buy a licence for the full version of Q, and get the DDR core license along with it, as well as other cores - the FIR and FFT cores might be of interest). When you buy these, you get a year's worth of upgrades and support, and a perpetual license for the cores. Of course, it might work out cheaper (depending on your volumes, and development times and costs) just to use two SDRAM chips and a faster clock, saving you the need to buy Q. Similarly, you might find a different cpu core such as Lattice's free core, or something from opencores, will do the same job.
Reply by ●June 5, 20082008-06-05
> I am not an expert on Altera licensing, but as far as I can tell you u=se => Quartus web edition and open core evaluation during development. This==> means you can use the DDR core (the sdram core is always free from => Altera, and runs a lot more than 50 MHz, as is their dma core) and the==> NIOS core while connected to Quartus with by jtag. For stand-alone us=e, => you have to buy a NIOS license and a DDR core license (in practice, yo=u => buy a licence for the full version of Q, and get the DDR core license ==> along with it, as well as other cores - the FIR and FFT cores might be==> of interest). When you buy these, you get a year's worth of upgrades ==> and support, and a perpetual license for the cores.Duhhhhhhhhh I missed the fact that the "free" NIOS was not free, thanks for pointin= g = this out !> Of course, it might work out cheaper (depending on your volumes, and => development times and costs) just to use two SDRAM chips and a fasterOr a 32 bit SDRAM which is what I had in mind initially.> clock, saving you the need to buy Q. Similarly, you might find a => different cpu core such as Lattice's free core, or something from => opencores, will do the same job.I have an escape route. If I include FireWire in the project (which now seems likely), then I c= an = use the ARM7 cpu which is in the DICE FireWire chip. I would have to = connect its bus to the FPGA, using lots of pins, but there are enough pi= ns = to do this. I think this is going to be the simplest way to pass the = licensing minefield. Now I am thinking about the memory interface : - DDR=3Dhard, SDR=3Deasy, - DDR=3D2.5V, SDR=3D3.3V, - We want some LVDS IO and lots of 3.3V IO, so we want one 2.5V bank, = Xilinx has 4 banks and Altera 8, so LVDS IO mandates DDR on Xilinx lest = a = lot of pins be wasted, not so on Altera because of the 8 banks, - But Altera Cyclone III has extremely tight tolerances on 3.3V because = of = the process used, I read on this group that actually it likes 3.0V bette= r, = and a little overshoot on 3.3V makes it latchup apparently. - This makes me uneasy to use Altera because there will be cables, and = cables =3D risks of overshoot...
Reply by ●June 5, 20082008-06-05
PFC wrote:> >> I am not an expert on Altera licensing, but as far as I can tell you >> use Quartus web edition and open core evaluation during development. >> This means you can use the DDR core (the sdram core is always free >> from Altera, and runs a lot more than 50 MHz, as is their dma core) >> and the NIOS core while connected to Quartus with by jtag. For >> stand-alone use, you have to buy a NIOS license and a DDR core license >> (in practice, you buy a licence for the full version of Q, and get the >> DDR core license along with it, as well as other cores - the FIR and >> FFT cores might be of interest). When you buy these, you get a year's >> worth of upgrades and support, and a perpetual license for the cores. > > Duhhhhhhhhh > I missed the fact that the "free" NIOS was not free, thanks for > pointing this out ! >Yes, you can use the Nios "freely" during development, and "freely" once you've paid the license :-) It's not unreasonable, actually - it's a one-off cost for a perpetual royalty-free license. But for a low-budget project, it's a significant cost.>> Of course, it might work out cheaper (depending on your volumes, and >> development times and costs) just to use two SDRAM chips and a faster > > Or a 32 bit SDRAM which is what I had in mind initially. > >> clock, saving you the need to buy Q. Similarly, you might find a >> different cpu core such as Lattice's free core, or something from >> opencores, will do the same job. > > I have an escape route. > If I include FireWire in the project (which now seems likely), then > I can use the ARM7 cpu which is in the DICE FireWire chip. I would have > to connect its bus to the FPGA, using lots of pins, but there are enough > pins to do this. I think this is going to be the simplest way to pass > the licensing minefield. >If you have an external processor connected anyway, you can also save a bit by using the processor to download the FPGA configuration - no need for a configuration flash, and it's easier to update the fpga software in the field. I might also suggest an FTDI FT2232C USB device - you can use it to download software into an FPGA or a processor via SPI or UART, thus avoiding any flash at all on the card (if you are happy always being connected to a PC, of course).> Now I am thinking about the memory interface : > > - DDR=hard, SDR=easy, > - DDR=2.5V, SDR=3.3V, > - We want some LVDS IO and lots of 3.3V IO, so we want one 2.5V bank, > Xilinx has 4 banks and Altera 8, so LVDS IO mandates DDR on Xilinx lest > a lot of pins be wasted, not so on Altera because of the 8 banks, > - But Altera Cyclone III has extremely tight tolerances on 3.3V because > of the process used, I read on this group that actually it likes 3.0V > better, and a little overshoot on 3.3V makes it latchup apparently. > - This makes me uneasy to use Altera because there will be cables, and > cables = risks of overshoot...Look carefully at the Altera application notes for how to use 3.3V safely on the CIII - don't just accept the word of a Xilinx employee! (I'm not accusing anyone in c.a.f. of lying - but you can't except a X employee to go out of their way to put Altera devices in the best light.) I haven't used a CIII yet, so I have no experience here.
