which commercial HDL-Simulator for FPGA?

As commodity PC hardware and prouctivity applications deline in price, EDA 
tools are as (relatively) expensive as ever, necessitating yet another 
discussion of "Which simulator is right for me?"

The contendors are ...

1) Aldec Active-HDL
   + great design-flow assistants (state-diagram, block-diagram,
      waveform-diagram editing, export to PDF)
   + possibly faster than Modelsim/PE?
   - no direct support in FPGA design-suites (Webpack/Quartus)
   - Windoze only (can WINE 1.0 run it?)
   - Systemverilog is almost but not quite usable ('package' not 
supported?!?)
   "less than $6000 for mixed-lang. VHDL+Verilog simulation"
     (Note, that configuration is the most basic, doesn't have 
SWIFT/Smartmodel)
    [first year pepetual-license, yearly maint. is additional 20%/year]

2) Mentor Modelsim PE
  + currently more solid Systemverilog support than Active-HDL,
      (but limited to design-constructs, no assertions/coverage)
  + de-facto industry standard,
     direct integration into FPGA design-suites (Webpack/Quartus)
  + SWIFT/Smartmodel support (no extra cost if using mixed-HDL license)
  - I really don't like the integrated waveform viewer
  - Windoze only (can WINE 1.0 run it?)
   "less than $10,000 for mixed-lang. VHDL+Verilog simulation"
    [first year perpetual-license, yearly maint. is additional 20%/year]

3) FPGA-vendor OEM solution (usually a crippled Modelsim/PE)
   + cheapest
   + Altera Modelsim officially supports Linux (Xilinx does not)
   + Xilinx Modelsim has same level of (design construct) Systemverilog
       support as Modelsim/PE, quite good actually
   - limited capacity, deliberately slower runtime performance
   - term-based only (no perpetual license for Xilinx/Altera?)
   - no mixed-HDL (VHDL+Verilog)  -- deal-killer for me...
   "less than $1500 for 1-language, 1-year license"

If I only had to do 'abstract' RTL-design (algorithm proof, no 
device-dependent instantiations...)

*4) gHDL, Icarus Verilog
    + free, open-source VHDL, Verilog
    - emacs/gvim not included
    - no mixed-HDL (VHDL+Verilog) sim

.............

Kidding aside, my real requirements:

1) I foresee mixed-HDL as a *requirement* for any serious consulting job. 
(Xilinx and Altera are pretty good about providing  'HDL-neutral IP', but 
third-parties aren't.)

2) ASIC sign-off is obviously not a concern -- who's going to compete with a 
professional turn-key bureau?

3) Design-size (capacity) is an unknown.  For front-end (RTL) simulation, I 
think even the OEM Modelsims are adequate.  But for gate-level, that might 
push them over the limit.  It's interesting that even a 'budget' <$500 
FPGA-board already has sufficient gate-capacity to overwhelm a 
single-designer...progress!

3) validation/qualification with fpga vendor. I like Active-HDL's 
user-interface more than Modelsim, but I can't escape the fact that 
Modelsim/PE has wider industry endorsement.  It's hard to argue with the 
management types who're more interested in checkboxes than the less 
tangibles  (oh ... like ... employee productivity?)

Finally, I note the irony of Modelsim/Altera and Modelsim/Xilinx editions. 
Altera Quartus-II supports Systemverilog synthesis, quite well, actually. 
But Altera's Modelsim is based on the aging 6.1g version, which is 
regrettably limited.  Xilinx Webpack doesn't support Systemverilog, but 
their Modelsim/XE is based on the more recent 6.3c codebase.  I find it 
useful for testbenching, though too many colleagues heckle me for my 
systemverilog "religion."  (I believe in it, and so should they.) 

SynopsysFPGAexpress wrote:
> As commodity PC hardware and prouctivity applications deline in price, EDA 
> tools are as (relatively) expensive as ever, necessitating yet another 
> discussion of "Which simulator is right for me?"

This reads like a thinly veiled marketing survey.

If you actually are a designer,
get a proto design ready,
order evals of each simulator
then try them and see for yourself.

> Kidding aside, my real requirements:
Which part were you kidding about?

> 1) I foresee mixed-HDL as a *requirement* for any serious consulting job. 
> (Xilinx and Altera are pretty good about providing  'HDL-neutral IP', but 
> third-parties aren't.)

The device vendors are only HDL-neutral because
they are selling device netlists, not source code.
Not a plus in my book.

  -- Mike Treseler

On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"
<fpgas@sss.com> wrote:

>As commodity PC hardware and prouctivity applications deline in price, EDA 
>tools are as (relatively) expensive as ever, necessitating yet another 
>discussion of "Which simulator is right for me?"
>
>The contendors are ...

Don't forget http://fintronic.com/home.html and 
http://simucad.com/products/verilogSimulation/silos-x.html

I personally like Finsim (from Fintronic) a lot. It's a compiled
simulator and it's quite fast.

On Wed, 18 Jun 2008 23:38:42 -0700, Muzaffer Kal <kal@dspia.com> wrote:

>On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"
><fpgas@sss.com> wrote:
>
>>As commodity PC hardware and prouctivity applications deline in price, EDA 
>>tools are as (relatively) expensive as ever, necessitating yet another 
>>discussion of "Which simulator is right for me?"
>>
>>The contendors are ...
>
>Don't forget http://fintronic.com/home.html and 
>http://simucad.com/products/verilogSimulation/silos-x.html
>
>I personally like Finsim (from Fintronic) a lot. It's a compiled
>simulator and it's quite fast.

Both appear to fail the OP's requirements (and mine); 
they look to be Verilog only.

- Brian

On Jun 18, 11:38 pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 18 Jun 2008 18:01:59 -0700, "SynopsysFPGAexpress"
>
> <fp...@sss.com> wrote:
> >As commodity PC hardware and prouctivity applications deline in price, EDA
> >tools are as (relatively) expensive as ever, necessitating yet another
> >discussion of "Which simulator is right for me?"
>
> >The contendors are ...
>
> Don't forgethttp://fintronic.com/home.htmlandhttp://simucad.com/products/verilogSimulation/silos-x.html
>
> I personally like Finsim (from Fintronic) a lot. It's a compiled
> simulator and it's quite fast.

I've been using Veritak, a low cost Veritak simulator.  It has had
some bugs, but the author
is VERY quick to fix problems.  A surprise - he is also VERY
responsive to requests for
new features or enhancements.  I'm very pleased with his product.

John Providenza

SynopsysFPGAexpress wrote:
> As commodity PC hardware and prouctivity applications deline in price, EDA 
> tools are as (relatively) expensive as ever, necessitating yet another 
> discussion of "Which simulator is right for me?"
> 
> The contendors are ...
...
> 

If you have Xilinx ISE 10.1, check out ISIM, which comes "free" with it. 
  It's much improved and may meet your needs and in future releases 
should have better a better user interface.  I don't think it currently 
supports SystemVerilog, (and you are correct in propagating your 
religion) but might soon.  Modelsim is still the best, but you pay for a 
lot of things you don't really need, and the waveform viewer could be 
improved.  That's where you spend 90% of your time during debugging so 
it should be a little easier to use.
-Kevin

In article <g3e8sk$ssv1@cnn.xsj.xilinx.com>,
Kevin Neilson  <kevin_neilson@removethiscomcast.net> wrote:
>...  Modelsim is still the best, but you pay for a 
>lot of things you don't really need, and the waveform viewer could be 
>improved.  That's where you spend 90% of your time during debugging so 
>it should be a little easier to use.

I've used vcs and currently have access to ncsim, so I've not bothered with
modelsim.  However, recently I tried the free one which comes with Altera
web edition.

So in either of these, you typically simulate and have all signals dumped to
a huge output file (using $dumpvars(0); $dumpon; for vcs or $shm_open(...);
$shm_probe(..); for ncsim).  Then you can explore the design hierarchy and
choose which signals to view in vcs -RPP or simvision.  The same is true for
even icarus verilog with gtkwave.

However with modelsim it looks like there is no way to do this.  Instead,
when you add a signal to the viewer in the GUI, it re-runs the entire
simulation to get the new signal.  Am I missing something or is this really
how it works?  I can't believe that it would really work this way.

(Also the crippled free modelsim is slower than icarus).

Has anyone tried to simulate Altera's IP with icarus?  I'm thinking about
the .vo simulation model of the altmemphy DDR controller.

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

On Thu, 19 Jun 2008 19:27:10 +0000 (UTC)
jhallen@TheWorld.com (Joseph H Allen) wrote:

> However with modelsim it looks like there is no way to do this.
> Instead, when you add a signal to the viewer in the GUI, it re-runs
> the entire simulation to get the new signal.  Am I missing something
> or is this really how it works?  I can't believe that it would really
> work this way.

Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf
"mydump.wlf", and you'll get similar results (just in a different
format). In my experience ncsim is faster than Modelsim, and of course
it carries a higher price tag.

Older versions of Modelsim also seems to stall after long simulations,
wehreas ncsim never gave me any problems.

-- 
Faster, faster, you fool, you fool!
		-- Bill Cosby

In article <20080619124737.4526bf02@wolfenstein.jpl.nasa.gov>,
Jason Zheng  <Xin.Zheng@jpl.nasa.gov> wrote:

>Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf
>"mydump.wlf", and you'll get similar results (just in a different
>format). In my experience ncsim is faster than Modelsim, and of course
>it carries a higher price tag.

This didn't work, but I eventually figured it out:

Start with an empty directory except for some verilog files you want to
simulate:

# Create work directory
vlib work

# Compile verilog files (vcom for vhdl)
vlog tb.v
vlog dut.v

# Simulate
vsim -do "log -r *; run -all; quit -f" work.tb

   - this creates a vsim.wlf file with everything in it just
     as you say.

Now try to view the waveform.  If I try:

vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"

This brings up modelsim GUI and opens the waveform viewer window.  All of
signals are in the viewer, and they're all empty.

But this does work:

vsim -view vsim.wlf -do "view wave; add wave *"

but it won't work after you have done the previous vsim -wlf command, vsim
-wlf does something to the .wlf file or sets something in an initialization
file somewhere.  I had to re-run the simulation before "vsim -view ..." for
it to work.


BTW, I notice that if I do add

  initial
    begin
      $dumpvars(0);
      $dumpon;
      ...
    end

vsim will generate a dump.vcd file, and I can use gtkwave to view it just
fine.  I had thought this didn't work, I guess I was wrong or something
changed recently.  Maybe I should just forget about using modelsim's
built-in viewer.

I notice that when the GUI is open, I can't also run a simulation on the
command line because there is only one license.

This is modelsim 6.1g which comes with Quartus 8.0 web edition running under
windows.

-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

On 18 juin, 21:01, "SynopsysFPGAexpress" <fp...@sss.com> wrote:
> As commodity PC hardware and prouctivity applications deline in price, EDA
> tools are as (relatively) expensive as ever, necessitating yet another
> discussion of "Which simulator is right for me?"
>
> The contendors are ...
>
> 1) Aldec Active-HDL
>    + great design-flow assistants (state-diagram, block-diagram,
>       waveform-diagram editing, export to PDF)
>    + possibly faster than Modelsim/PE?
>    - no direct support in FPGA design-suites (Webpack/Quartus)
>    - Windoze only (can WINE 1.0 run it?)
>    - Systemverilog is almost but not quite usable ('package' not
> supported?!?)
>    "less than $6000 for mixed-lang. VHDL+Verilog simulation"
>      (Note, that configuration is the most basic, doesn't have
> SWIFT/Smartmodel)
>     [first year pepetual-license, yearly maint. is additional 20%/year]

One vote for Active-HDL. I briefly used Modelsim before we bought
Active-HDL and for me anyway, the Active-HDL interface is much better.
It's true that it's not officially supported by Xilinx but in practice
that really never caused too much of a problem.

I really like to create a schematic top level with blocks that are
either more schematics themselves or directly vhdl blocks. That way
it's much easier to see how everything connects together, it helps
comprehension. I don't quite understand why some people insist on
writing direct VHDL connections between blocks. It's a little bit like
insisting on writing pspice netlists for simulations instead of using
the schematic editor. Active-HDL converts schematics to vhdl code
anyway, so it's never too late to go back to vhdl-only code. The
resulting code will be very clean if you keep your top level free of
logic.

The state-machine editor in Active-HDL is another story. To me simple
state machines don't need to be represented by a diagram to be
understood. On the other hand, large ones are hard to represent in a
diagram. So in the end I only write vhdl state machines.

Patrick