Forums

Altera, Cyclone III, PCI, LVCMOS, & 3.3V

Started by bob elkind June 21, 2008
Quick summary:  Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ?

I've read Altera apnote AN447 http://www.altera.com/literature/an/an447.pdf  I understand this apnote to suggest that any/all 3.3V 
LVTTL or LVCMOS signals connected to a Cyclone III must employ series termination.  (Assumptions for my design: 3.3V VCCIO on the 
Cyclone III, and the signal source is *not* configurable to moderate rise/fall time)

This seems rather bizarre.  At first I thought this applied only to PCI, rather than straight 3.3V LVTTL and LVCMOS, because the 
open-system PCI spec requires tolerance of nasty overshoots.  This would be easy to waive off, as I'm not designing an open PCI 
system, just 6" PCI using 3.3V 5% supplies.  But no, it seems that Altera is requiring a new and unique supply voltage for all 
3.3V (the predominant signaling standard in my designs).

Other than reverting to Cyclone II or Xilinx devices for my current design, are there any other options?  External Schottky clamp 
diodes to 3.3V at each end of the bus ?  Parallel termination at each end of the bus ?

I cringe at using 3.0V VCCIO.  First, I'll need linear LDOs at each device.  Then there's the due diligence work to ensure there 
are no unforseen "collateral damages" from 3.0V devices talking to 3.3V devices (e.g. what supply do you use for pullup resistors 
?) -- I appreciate the old maxim: "I don't know what I don't know".

I regret starting this design with three Cyclone IIIs on the board.  Unless the bird of Altera Paradise lands on my head to soothe 
me, I'll seek other options going forward.

Thanks in advance for any words of wisdom and advice.  Please post followups in this newsgroup!

- Bob Elkind 


Some of my colleagues have designed complex PC type controller boards 
(PCI interfaces) where many different voltages are needed. In these 
cases, a complex switching power supply design is utilized and deriving 
one more voltage isn't too much of an issue.

By the way, there were a couple of recent discussions on this newsgroup 
about this topic titled, "Cyclone 3 on chip termination" and "Cyclone 3 
margins: none at all at 3.3v"

For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for 
normal LVTTL type interface you can use 3.3V, I've done it.  You just 
have to make darn sure that your transmission lines are designed properly.

Take care,
Rob





bob elkind wrote:
> Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? > > I've read Altera apnote AN447 http://www.altera.com/literature/an/an447.pdf I understand this apnote to suggest that any/all 3.3V > LVTTL or LVCMOS signals connected to a Cyclone III must employ series termination. (Assumptions for my design: 3.3V VCCIO on the > Cyclone III, and the signal source is *not* configurable to moderate rise/fall time) > > This seems rather bizarre. At first I thought this applied only to PCI, rather than straight 3.3V LVTTL and LVCMOS, because the > open-system PCI spec requires tolerance of nasty overshoots. This would be easy to waive off, as I'm not designing an open PCI > system, just 6" PCI using 3.3V 5% supplies. But no, it seems that Altera is requiring a new and unique supply voltage for all > 3.3V (the predominant signaling standard in my designs). > > Other than reverting to Cyclone II or Xilinx devices for my current design, are there any other options? External Schottky clamp > diodes to 3.3V at each end of the bus ? Parallel termination at each end of the bus ? > > I cringe at using 3.0V VCCIO. First, I'll need linear LDOs at each device. Then there's the due diligence work to ensure there > are no unforseen "collateral damages" from 3.0V devices talking to 3.3V devices (e.g. what supply do you use for pullup resistors > ?) -- I appreciate the old maxim: "I don't know what I don't know". > > I regret starting this design with three Cyclone IIIs on the board. Unless the bird of Altera Paradise lands on my head to soothe > me, I'll seek other options going forward. > > Thanks in advance for any words of wisdom and advice. Please post followups in this newsgroup! > > - Bob Elkind > >
Some of my colleagues have designed complex PC type controller boards 
(PCI interfaces) where many different voltages are needed. In these 
cases, a complex switching power supply design is utilized and deriving 
one more voltage isn't too much of an issue.

By the way, there were a couple of recent discussions on this newsgroup 
about this topic titled, "Cyclone 3 on chip termination" and "Cyclone 3 
margins: none at all at 3.3v"

For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for 
normal LVTTL type interface you can use 3.3V, I've done it.  You just 
have to make darn sure that your transmission lines are designed properly.

Take care,
Rob

bob elkind wrote:
> Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? > > I've read Altera apnote AN447 http://www.altera.com/literature/an/an447.pdf I understand this apnote to suggest that any/all 3.3V > LVTTL or LVCMOS signals connected to a Cyclone III must employ series termination. (Assumptions for my design: 3.3V VCCIO on the > Cyclone III, and the signal source is *not* configurable to moderate rise/fall time) > > This seems rather bizarre. At first I thought this applied only to PCI, rather than straight 3.3V LVTTL and LVCMOS, because the > open-system PCI spec requires tolerance of nasty overshoots. This would be easy to waive off, as I'm not designing an open PCI > system, just 6" PCI using 3.3V 5% supplies. But no, it seems that Altera is requiring a new and unique supply voltage for all > 3.3V (the predominant signaling standard in my designs). > > Other than reverting to Cyclone II or Xilinx devices for my current design, are there any other options? External Schottky clamp > diodes to 3.3V at each end of the bus ? Parallel termination at each end of the bus ? > > I cringe at using 3.0V VCCIO. First, I'll need linear LDOs at each device. Then there's the due diligence work to ensure there > are no unforseen "collateral damages" from 3.0V devices talking to 3.3V devices (e.g. what supply do you use for pullup resistors > ?) -- I appreciate the old maxim: "I don't know what I don't know". > > I regret starting this design with three Cyclone IIIs on the board. Unless the bird of Altera Paradise lands on my head to soothe > me, I'll seek other options going forward. > > Thanks in advance for any words of wisdom and advice. Please post followups in this newsgroup! > > - Bob Elkind > >
"Rob" <buzoff@leavemealone.com> wrote in message news:485DC7BF.9030200@leavemealone.com...
...
> For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for normal LVTTL type interface you can use 3.3V, I've done > it. You just have to make darn sure that your transmission lines are designed properly. > > Take care, > Rob
Rob, what's the difference between PCI and 3.3V LVTTL, that one requires 3.0V and the other does not ? - Bob Elkind
I've never personally designed with PCI but Austin made note in the 
previous discussion that:

"PCI at 3.3V REQUIRES reflective wave switching.  That means
the inputs have overshoot and undershoot BY DESIGN."

Rob



bob elkind wrote:
> "Rob" <buzoff@leavemealone.com> wrote in message news:485DC7BF.9030200@leavemealone.com... > ... >> For PCI, the recommendation is to use 3.0V at the VCCIO pins; but for normal LVTTL type interface you can use 3.3V, I've done >> it. You just have to make darn sure that your transmission lines are designed properly. >> >> Take care, >> Rob > > Rob, what's the difference between PCI and 3.3V LVTTL, that one requires 3.0V and the other does not ? > > - Bob Elkind > >
Rob wrote:
> I've never personally designed with PCI but Austin made note in the > previous discussion that: > > "PCI at 3.3V REQUIRES reflective wave switching. That means > the inputs have overshoot and undershoot BY DESIGN." > > Rob
And that should be fine as long as the overshoot falls within the acceptable range of the FPGA such as that defined by the Altera Cyclone III Device Datasheet: DC and Switching Characteristics, table 1-2, right? Big table, second page, hard to miss (at least for some readers). There's an added advantage for modern CMOS drivers that are actively driving the line: not only does the PCI clamp help out but the driver actively pulls reflections back *down* to the positive rail when driving logic high; FETs are bidirectional, after all, and the IBIS models show the data to support this. It's the non-driving FPGA I/Os that are subject to the reflective wave that are under the greatest stress. Even then, however, short PCI busses don't overdrive long enough to create problems for many lower speed signals like PCI. Add other devices along the path and you have other PCI clamps adding together to tame the reflections. I'd appreciate any feedback on this perspective. Engineering discussions often fall on deaf ears when application notes or data sheets say "don't do this" even though it's followed with "unless you perform due diligence." - John_H