Newbie Verilog Question / ModelSim

Hi,

I am thinking of using Verilog for a project I am working on. Originally 
I was going to use a processor core (and C) on an environment someone 
set up for me in VHDL/Verilog, then I thought of using FpgaC and doing 
it myself, and now I'm more or less decided on using Verilog to do most 
of it (minus the hardware stuff, after initial development and simulation).

My first questions, of which I hope there won't be many, relate to 
connecting 'wires' between modules, and simulations.

In my code I am attempting to change a value of 'addr' in setaddr to a 
specific value when processing starts, this will later be set by an 
address switch on the hardware. I am then trying to match this value in 
another module called decpacket when 'pktrx' changes, when a packet 
comes in (code not written for serial communications).

In ModelSim, the simulator shows that 'addr' in decpacket is 8 bits 
wide, but for some reason 'addr' in setaddr is only shown as a single 
bit. Could someone kindly point out what I am doing wrong, and how I can 
set this value in one location and use it in another?

Thanks,

RL


`timescale 1ns / 100ps

module setaddr(addr);

     output[0:7] addr;
     reg addr;

    initial begin
       addr = 8'd 1;
    end

endmodule

module decpacket (addr,pktrx,pkt,pkttype);

     input[0:7] addr;
     input pktrx;
     input[0:95] pkt;
     output[0:7] pkttype;

     reg pkttype;

     always @(posedge pktrx)
     begin
        if(pkt[0:7] == addr)
        begin

        end
     end

endmodule

On Sun, 22 Jun 2008 16:43:17 +1200, RL <rl@null.void.test> wrote:
>My first questions, of which I hope there won't be many, relate to 
>connecting 'wires' between modules, and simulations.
>
I'm afraid, by looking at your first question, you'll have many more;
which is OK but asking all of them to the Internet may not be the most
efficient way to get them answered. Maybe a Verilog book?

>In ModelSim, the simulator shows that 'addr' in decpacket is 8 bits 
>wide, but for some reason 'addr' in setaddr is only shown as a single 
>bit. Could someone kindly point out what I am doing wrong, and how I can 
>set this value in one location and use it in another?
>
>Thanks,
>
>RL
>
>
>`timescale 1ns / 100ps
>
>module setaddr(addr);
>
>     output[0:7] addr;
>     reg addr;
Here you need to change the reg to 8 bits too:

reg [0:7] addr;

>
>    initial begin
>       addr = 8'd 1;
>    end
>
>endmodule
>
the way to connect setaddr & decpacket is to instantiate both of them
and connect the addr wires to each other ie

wire [0:7] addr;

setaddr   u0(.addr(addr));
decpacket u1(.addr(addr)...);

>module decpacket (addr,pktrx,pkt,pkttype);
>
>     input[0:7] addr;
>     input pktrx;
>     input[0:95] pkt;
>     output[0:7] pkttype;
>
>     reg pkttype;
>
>     always @(posedge pktrx)
>     begin
>        if(pkt[0:7] == addr)
>        begin
>
>        end
>     end
>
>endmodule

Muzaffer Kal wrote:
> On Sun, 22 Jun 2008 16:43:17 +1200, RL <rl@null.void.test> wrote:
>> My first questions, of which I hope there won't be many, relate to 
>> connecting 'wires' between modules, and simulations.
>>
> I'm afraid, by looking at your first question, you'll have many more;
> which is OK but asking all of them to the Internet may not be the most
> efficient way to get them answered. Maybe a Verilog book?

Thanks for your assistance. I'll give it a try when I get time (tomorrow 
afternoon).

I've been looking around for good tutorials, but unfortunately most seem 
to assume I come from an electronics background. Books will likely have 
a similar focus.

Fortunately what I need to do isn't particularly complicated. It is very 
basic serial communications and simple data manipulation, so basic 
Verilog should get me a long way. If I do make some progress, and am 
comfortable working with hardware concepts (I come from a C development 
background), then I'll probably end up buying a book to further my 
knowledge.

Thanks,

RL

On Jun 21, 11:37 pm, RL <r...@null.void.test> wrote:
> Muzaffer Kal wrote:
> > On Sun, 22 Jun 2008 16:43:17 +1200, RL <r...@null.void.test> wrote:
> >> My first questions, of which I hope there won't be many, relate to
> >> connecting 'wires' between modules, and simulations.
>
> > I'm afraid, by looking at your first question, you'll have many more;
> > which is OK but asking all of them to the Internet may not be the most
> > efficient way to get them answered. Maybe a Verilog book?
>
> Thanks for your assistance. I'll give it a try when I get time (tomorrow
> afternoon).
>
> I've been looking around for good tutorials, but unfortunately most seem
> to assume I come from an electronics background. Books will likely have
> a similar focus.
>
> Fortunately what I need to do isn't particularly complicated. It is very
> basic serial communications and simple data manipulation, so basic
> Verilog should get me a long way. If I do make some progress, and am
> comfortable working with hardware concepts (I come from a C development
> background), then I'll probably end up buying a book to further my
> knowledge.
>
> Thanks,
>
> RL

You may want to take a look at some example designs to get an idea of
how to code
in Verilog.  Opencores has lots of projects that you can look at.
Bear in mind that the
quality of the projects vary, so don't take them as gospel - use them
to get a flavor
of what's required.

Something beginners don't realize is that some Verilog constructs
don't synthesize into
hardware - they're mainly used for simulations.

Good luck!

John Providenza

On Jun 22, 8:36 am, jprovide...@yahoo.com wrote:
> On Jun 21, 11:37 pm, RL <r...@null.void.test> wrote:
>
>
>
> > Muzaffer Kal wrote:
> > > On Sun, 22 Jun 2008 16:43:17 +1200, RL <r...@null.void.test> wrote:
> > >> My first questions, of which I hope there won't be many, relate to
> > >> connecting 'wires' between modules, and simulations.
>
> > > I'm afraid, by looking at your first question, you'll have many more;
> > > which is OK but asking all of them to the Internet may not be the most
> > > efficient way to get them answered. Maybe a Verilog book?
>
> > Thanks for your assistance. I'll give it a try when I get time (tomorrow
> > afternoon).
>
> > I've been looking around for good tutorials, but unfortunately most seem
> > to assume I come from an electronics background. Books will likely have
> > a similar focus.
>
> > Fortunately what I need to do isn't particularly complicated. It is very
> > basic serial communications and simple data manipulation, so basic
> > Verilog should get me a long way. If I do make some progress, and am
> > comfortable working with hardware concepts (I come from a C development
> > background), then I'll probably end up buying a book to further my
> > knowledge.
>
> > Thanks,
>
> > RL
>
> You may want to take a look at some example designs to get an idea of
> how to code
> in Verilog.  Opencores has lots of projects that you can look at.
> Bear in mind that the
> quality of the projects vary, so don't take them as gospel - use them
> to get a flavor
> of what's required.
>
> Something beginners don't realize is that some Verilog constructs
> don't synthesize into
> hardware - they're mainly used for simulations.
>
> Good luck!
>
> John Providenza

You may be able to take free online courses at the FPGA/CPLD vendor
whose part you have on your board...
e.g. http://www.altera.com/education/training/courses/OHDL1120

Just a reminder though - when you design something meaningful with
verilog you are designing hardware and not software.  So very soon it
will help you to also pick up the fundamentals of the digital logic
design and hardware design practices otherwise it can get to be very
frustrating.