virtex-5: can't use DCM (too low input frequency)

Hi all,
I have a camera and a Virtex-5 FPGA, and i would like to store frames
in FPGA Block Ram.
In my design (that worked with Spartan-3E) i need to double camera
clock frequency, in order to get all data, because camera send data on
both clock edges.
The problem is the following: I can't use DCM, because camera clock
frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
"DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
Mode Range is 1-40 Mhz".
How can I avoid this problem? Do you think that I could use component
DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
Multiplier that works fine?

Giulio

On Jun 22, 6:20=A0pm, techG <giuliopul...@gmail.com> wrote:
> In my design (that worked with Spartan-3E) i need to double camera
> clock frequency, in order to get all data, because camera send data on
> both clock edges.

Have you looked into DDR flip-flops? Those should allow you to read
data coming in on both clock edges at the regular clock frequency.
Check out the Virtex 5 IDDR input primitive.

Regards,
-- Hauke D

techG wrote:
> Hi all,
> I have a camera and a Virtex-5 FPGA, and i would like to store frames
> in FPGA Block Ram.
> In my design (that worked with Spartan-3E) i need to double camera
> clock frequency, in order to get all data, because camera send data on
> both clock edges.
> The problem is the following: I can't use DCM, because camera clock
> frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> Mode Range is 1-40 Mhz".
> How can I avoid this problem? Do you think that I could use component
> DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> Multiplier that works fine?
>
> Giulio

Hi Giulio,
So, your input frequency is 6MHz. The wizard tells you that "DFS Low 
Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps 
you should use your DCM in DFS Low Frequency Mode.
HTH., Syms.
p.s It's Hz not hz. 

On Jun 22, 1:48=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
> techG wrote:
> > Hi all,
> > I have a camera and a Virtex-5 FPGA, and i would like to store frames
> > in FPGA Block Ram.
> > In my design (that worked with Spartan-3E) i need to double camera
> > clock frequency, in order to get all data, because camera send data on
> > both clock edges.
> > The problem is the following: I can't use DCM, because camera clock
> > frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> > DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> > "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> > Mode Range is 1-40 Mhz".
> > How can I avoid this problem? Do you think that I could use component
> > DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> > Multiplier that works fine?
>
> > Giulio
>
> Hi Giulio,
> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perh=
aps
> you should use your DCM in DFS Low Frequency Mode.
> HTH., Syms.
> p.s It's Hz not hz.

If I remember right (I am at home on this beautiful sunday) the output
frequency then must be above 19 MHz.
So you would have to multiply by 4 and then use a flip-flp to divide
by 2.

The suggested use of the DDR input seems to be best, it gives you two
parallel bits at the 6 MHz frequency. If you prefer 12 MHz, I could
mention "my" frequency doubler from "six easy pieces".

There are several solutions...
Peter Alfke

On Jun 22, 10:48=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
> Hi Giulio,
> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perh=
aps
> you should use your DCM in DFS Low Frequency Mode.
> HTH., Syms.
> p.s It's Hz not hz.

I believe the problem is that the clock doubler is one of the DLL (not
DFS) outputs, where the minimum input frequency, even in low frequency
mode, is 19 MHz.

Regards,
-- Hauke D

Hauke D wrote:
> On Jun 22, 10:48 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>> Hi Giulio,
>> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
>> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40.
>> Perhaps you should use your DCM in DFS Low Frequency Mode.
>> HTH., Syms.
>> p.s It's Hz not hz.
>
> I believe the problem is that the clock doubler is one of the DLL (not
> DFS) outputs, where the minimum input frequency, even in low frequency
> mode, is 19 MHz.
>
> Regards,
> -- Hauke D

I see your point. I suggest multiplying by 4 and then dividing by two using 
clock enables in the fabric.
Cheers, Syms. 

On Jun 22, 10:48 pm, "Symon" <symon_bre...@hotmail.com> wrote:
> techG wrote:
> > Hi all,
> > I have a camera and a Virtex-5 FPGA, and i would like to store frames
> > in FPGA Block Ram.
> > In my design (that worked with Spartan-3E) i need to double camera
> > clock frequency, in order to get all data, because camera send data on
> > both clock edges.
> > The problem is the following: I can't use DCM, because camera clock
> > frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> > DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> > "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> > Mode Range is 1-40 Mhz".
> > How can I avoid this problem? Do you think that I could use component
> > DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> > Multiplier that works fine?
>
> > Giulio
>
> Hi Giulio,
> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps
> you should use your DCM in DFS Low Frequency Mode.
> HTH., Syms.
> p.s It's Hz not hz.

Unfortunately, I can't use 2xClockOutput in DFS Low Frequency Mode :(
Thank you all for the help, I'll try both ways:
1) using a DCM and dividing the 4x output by two (can I use another
DCM for this purpose?)
2) using IDDR flip-flops

Giulio

On Jun 22, 5:05=A0pm, techG <giuliopul...@gmail.com> wrote:
> On Jun 22, 10:48 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>
>
>
> > techG wrote:
> > > Hi all,
> > > I have a camera and a Virtex-5 FPGA, and i would like to store frames
> > > in FPGA Block Ram.
> > > In my design (that worked with Spartan-3E) i need to double camera
> > > clock frequency, in order to get all data, because camera send data o=
n
> > > both clock edges.
> > > The problem is the following: I can't use DCM, because camera clock
> > > frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> > > DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> > > "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> > > Mode Range is 1-40 Mhz".
> > > How can I avoid this problem? Do you think that I could use component
> > > DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> > > Multiplier that works fine?
>
> > > Giulio
>
> > Hi Giulio,
> > So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> > Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Pe=
rhaps
> > you should use your DCM in DFS Low Frequency Mode.
> > HTH., Syms.
> > p.s It's Hz not hz.
>
> Unfortunately, I can't use 2xClockOutput in DFS Low Frequency Mode :(
> Thank you all for the help, I'll try both ways:
> 1) using a DCM and dividing the 4x output by two (can I use another
> DCM for this purpose?)
> 2) using IDDR flip-flops
>
> Giulio

Giulio, I would advise against using a second DCM: It creates
additional jitter, and it makes it reallycomplicated to solve your
inherent phasing problem:
When you multiply by 4 and then divide by 2, you have a 50% chance of
picking up a wrong phase relationship between your 6 and 12 MHz
clocks.  Here is one solution:
Use the 24 MHz clock to generate a delayed version of your 6 MHz
clock.
Then control your divide-by-2 flip-flop such that it can change state
only when both your 6 MHz signals have the same level. Use an XOR.
I think the DDR method, or "my" frequency doubler are better
solutions.
Peter Alfke

On 23 Jun., 00:02, Hauke D <hau...@zero-g.net> wrote:
> On Jun 22, 10:48=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
>
> > Hi Giulio,
> > So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> > Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Per=
haps
> > you should use your DCM in DFS Low Frequency Mode.
> > HTH., Syms.
> > p.s It's Hz not hz.
>
> I believe the problem is that the clock doubler is one of the DLL (not
> DFS) outputs, where the minimum input frequency, even in low frequency
> mode, is 19 MHz.

So?
Instead use the CLKFX output in maximum range mode to provide a 24MHz
clock and read
in the data on every second clock cycle. (Do NOT divide the clock
using DFFs, instead use clock enables).

Kolja Sulimma

Peter Alfke wrote:
> On Jun 22, 5:05 pm, techG <giuliopul...@gmail.com> wrote:
> I think the DDR method, or "my" frequency doubler are better
> solutions.
> Peter Alfke

Hi Peter,
The DDR method makes the logic more complicated. You have to deal with two 
samples every clock cycle.
As for "your" frequency doubler, in the right hands it can be a useful tool. 
However, with a simple synchronous solution available using a DCM, I 
wouldn't recommend this path, especially for beginners.
YMMV, Syms.