spying on signals in Quartus (newbie question)

Hi,

When debugging a design one can assign inside the VHDL code debug pins. 
However, if after compiling and everything I decide to look for some 
other signal of choice (that are not pins), in the simulation, QUARTUS 
will give me a list of uninteligible names. Is there any way around 
this? Signal Tap seems to work only with a physical FPGA via JTAG.

Thanks
Vadim

Vadim Rusu <vrusu@hep.uchicago.edu> wrote in message news:<c1fr6u$6ra$1@info4.fnal.gov>...
> Hi,
> 
> When debugging a design one can assign inside the VHDL code debug pins. 
> However, if after compiling and everything I decide to look for some 
> other signal of choice (that are not pins), in the simulation, QUARTUS 
> will give me a list of uninteligible names. Is there any way around 
> this? Signal Tap seems to work only with a physical FPGA via JTAG.
> 
> Thanks
> Vadim


Hi Vadim,

  This is a cut and paste from an earlier post. To preserve a
combinatorial node through synthesis, place and route, you should do
one of the following:

a) If it is a BDF (schematic file) or TDF (AHDL file), feed the signal
that you are interested in observing into a LCELL primitive, and give
the LCELL primitive an interesting name, so that you can find it when
you choose the Post Compilation filter in the node finder. You should
feed the output of the LCELL to where the signal wof interes was
previously connected.

b) If you are using VHDL or Verilog, consider using the keep
pragma/keyword. Its usage is described in the online help. Search for
"keep". The Verilog help panel is shown below:

------------------- keep usage in Verilog
-----------------------------------
A Verilog HDL language directive that directs Analysis & Synthesis to
keep a particular wire intact. You can use this language directive to
keep a combinational logic node so you can observe the node during
simulation or with the SignalTap&#4294967295; II Logic Analyzer.

You cannot use this language directive for nodes that have no fan-out.

To use the keep language directive, you can specify the keep language
directive in a comment that is on the same line as the register you
want Analysis & Synthesis to preserve. In the comment, precede the
language directive with the synthesis keyword.

For example, in the following code, the comment /* synthesis preserve
*/ directs Analysis & Synthesis to not minimize the keep_wire
register:

wire keep_wire /* synthesis keep */;

-------------------------------------------------------------------------------

You would search for keep_wire in the Mode Finder.

Hope this helps.

- Subroto Datta
Altera Corp.