Nintendo DS Screenshots / Video Capture

On Jul 1, 8:00 pm, Paul Urbanus <urbpub...@hotmail.com> wrote:

> I'm not a verilog person, but here's the basic functional flow.
>
> 1. Implement a counter with a count length of 263 (counts from 0 to
> 262). This will be used to determine the horizontal position of the pixels.
> 2. Detect either the rising or falling edge of VSYNC - pick one and only
> one edge.
> 3. Use the detected VSYNC edge to load your horizontal counter with a
> specific value, initially to zero. If your image is shifted horizontally
> after you grab a frame, then adjust this preload value to get the image
> properly horizontally positioned.
> 4. Implement a second counter which keeps track of the line number of
> the screen image. Clear this counter with the detected VSYNC edge
> generate in step 2.
> 5. Increment the vertical counter from step 4 whenever the horizontal
> counter value is 262 (max count).

Actually the simplest thing to do may be to do a one-dimensional
recording of as many bits as will fit in the SRAM, triggered by the
vsync.  Dump the whole thing over the serial port and sort it out with
software on the PC where you can more easily see what you are doing.
If this proves to be inadequate, you can then re-design the fpga logic
to do a more targeted aquisition based on what you've learned.  For
example, if there's a lot of dead time between lines (it's not a CRT
with a beam that needs to retrace, but I suppose this could still
occur) you'd be wasting memory recording that, but you might still
have enough.

I'd build a circuit that's 'armed' by any activity on the RS232 RxD
line, is 'triggered' by the VSYNC, and once it's data is available
dumps all of it over the RS232 TxD.  You can find example RS232
transmitters online, and in this case you don't need a real receiver
in the fpga, just something that you can arm by having your computer
send an arbitrary character to it, after which it will reply with the
next available frame.

>Thanks again chaps I'll keep you all updated so you can have a good
>chuckle at watching a noob stratch his head and do lots of stupid
>things :)!!!!!
>

Sorry for reviving an old thread, but I'm curious about how your project
went.  I need to start getting ready for my own senior design project (May
2011), and I'm thinking of something similar with the DS but not exactly
the same.  My goal would be to get an analog RGB/YPbPr output at 480i/p. 
Although getting the output is quite the task, my project's main focus
would be various selectable screen output modes.  For example:
Mode A) Top Screen only, 256 x 192 centered with black borders all around
Mode B) Bottom Screen only, 256 x 192 centered with black borders all
around
Mode C) Top Screen only, 256 x 192 resized to 640 x 480
Mode D) Top screen above Bottom screen, no gap between screens
Mode E) Top screen above Bottom screen, 64-line gap filled with
interpolated data from both screens and/or motion predicted pixels

and so forth....

This brings me to a few questions directed at anyone willing to answer. 
With all the extra DSP aspects of my desired features, would the Spartan-3
still be a good candidate for this project?  Or will I need something more
powerful?  I would like to be taking FFTs to help with the video scaling,
so I would prefer something capable of that.  But, I can avoid the
frequency domain altogether if the price difference for that capability is
too large.  Also, I would probably need to buffer more than one frame for
the gap interpolation, so wouldn't I need more RAM?  If I do need something
more powerful, then what is recommended?
I was actually looking at these two kits before I found this thread:
http://www.xilinx.com/products/devkits/HW-SPAR3A-SK-UNI-G.htm
http://www.xilinx.com/products/devkits/HW-SD1800A-DSP-SB-UNI-G.htm

Also, to add:
I've never used FPGAs before, but just like the author (of this thread) I'm
willing to put in most of my free time since I'm not able to take the FPGA
course at my school until Spring 2011 (which is too late).  A major goal of
this project is to learn about FPGAs.

Any tidbits of help on this would be greatly appreciated.  Thank you.