Hi, is the new ALUT architecture of stratix 2 patented ? I have looked at the US patent office but could not find such a patent. Thank you for your help.
Stratix 2 ALUT architecture patented ?
Started by ●February 24, 2004
Reply by ●February 24, 20042004-02-24
Lenz, I am sure that they have filed for their patents. Since it takes two or more years, we will just have to wait and see what it is that gets patented. How this is any different than f5/f6/f7/f8 muxes is also at issue: have they just "renamed" an already existing architecture? Do they now achieve the same packing that is already enjoyed by others? Austin
Reply by ●February 25, 20042004-02-25
Austin, As a general rule, Altera likes to avoid using this site as a marketing tool. Instead, we choose to focus just on relevant technical questions. However, since you brought it up, the question at hand: is the innovation in Stratix II just a renaming of the f5/f6/f7/f8 muxes in Virtex products? On the contrary, the Stratix II architecture represents a complete redesign of a programmable logic fabric. Recognizing the need for a more powerful and efficient approach than the 4LUT + register fabric that all mainstream FPGAs have relied on for years, Altera increased the capability and flexibility of the Stratix II logic with a larger and truly adaptive logic module (ALM). An ALM can efficiently implement one to two 6LUTs, any 5LUT and 3LUT combination, two 5LUTs (for almost any 2 functions), any two 4LUTs etc...all in a single logic block. (For more complete listing, look here: http://www.altera.com/products/devices/stratix2/features/architecture/st2-lut.html) Previous FPGA architectures have only had 4LUT capabilities without routing between multiple logic blocks. Virtex devices are really a 4LUT architecture with some MUXes (note that "variable LUT terminology" was only recently mentioned in a white paper but is not found in the data sheet). The f5/fX muxes are one way to emulate larger LUT functions, but this approach comes at the cost of multiple LC resources, routing structures between those LC's, and requires that the synthesis tool (or the designer) intelligently map to those muxes. Analysis of synthesis and place and route results, suggests the f5/fX resources are commonly used in large distributed memory functions and wide muxes, but rarely benefit wide LUT functions. Comparing results of how real designs synthesize and map to Stratix II ALMs vs. Virtex-II Pro slices (the most direct comparison since each ALM/slice is capable of 2 4LUT functions) shows a 54% efficiency advantage for Stratix II. This increased logic efficiency also results in better performance and lower power, since with more logic density inside each logic block, less routing circuitry is used which tends to be slower and leakier by comparison. For those of you curious to find out more details on this, the following white paper and web seminar may interest you:. Logic Structure Comparison Between Stratix & Virtex-Based Architectures http://www.altera.com/literature/wp/wpstxiixlnx.pdf http://www.altera.com/education/net_seminars/current/stratix2/ns-stratix2.html?f=sx2hp&k=g2 Mike Rather Altera Corp. Austin Lesea <austin@xilinx.com> wrote in message news:<c1gfrh$l613@cliff.xsj.xilinx.com>...> Lenz, > > I am sure that they have filed for their patents. Since it takes two or > more years, we will just have to wait and see what it is that gets patented. > > How this is any different than f5/f6/f7/f8 muxes is also at issue: have > they just "renamed" an already existing architecture? Do they now > achieve the same packing that is already enjoyed by others? > > Austin
Reply by ●February 25, 20042004-02-25
Michael, Since you popped your head over the parapet... :) What's the story on MAX II Devices ?. There was glossary, timing and lib files gradually appearing, and suddenly the Altera web is cleansed and it's like MAX II is now 'off the radar' ?. Would seem to indicate some problems..... -jg
Reply by ●February 26, 20042004-02-26
Michael, Thank you very much. I have read all of the publicly available materials, and am still puzzled by the claims. Any claims of remarkable efficiency, you may understand, I am quite leary of. For example, if the claim of a St2 50% speed improvement is really true, then our demonstrated 40% speed improvement on average in the i6.2 release makes St2 only 10% faster than our 2 year old V2 Pro.....lowest speed grade. So leaving marketing to those who enjoy it, I will forego any claims of performance, and just ask about architecture. I was unclear on just how a ALM is any different from drawing the box differently around the components. I am still puzzled, but the block diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it was actually designed this way then that is simply what it is. A true 6 LUT has 64 memory cells and the associated logic, and two of these seems a bit excessive and would not require any other logic or muxes at all. Combining existing 4 LUTs to deliver some of the possible terms of a 6 LUT is a completely different matter. Regardless, it is enjoyable to hear about any radical or innovative new architecture, as there are so many that now dot the landscape as dead skeletons of past FPGAs. Austin
Reply by ●February 26, 20042004-02-26
Austin, I agree that performance claims will have to wait, but Jesse Kempa posted the LE results for a Nios softcore on Stratix I vs. II. The numbers showed just north of 30% fewer LE's used. Perhaps you (or someone else) could get your hands on an early version of Quartus II v4 and build some of your own designs and see for yourself. I'm sure everyone here would be interested in the results. Maybe someone from Altera would be willing to do it for you. It would be best for someone to use real world designs that they already have ported to both X and A. Ken "austin" <austin@xilinx.com> wrote in message news:c1jt6i$72u1@cliff.xsj.xilinx.com...> Michael, > > Thank you very much. I have read all of the publicly available > materials, and am still puzzled by the claims. > > Any claims of remarkable efficiency, you may understand, I am quite > leary of. For example, if the claim of a St2 50% speed improvement is > really true, then our demonstrated 40% speed improvement on average in > the i6.2 release makes St2 only 10% faster than our 2 year old V2 > Pro.....lowest speed grade. So leaving marketing to those who enjoy it, > I will forego any claims of performance, and just ask about architecture. > > I was unclear on just how a ALM is any different from drawing the box > differently around the components. I am still puzzled, but the block > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it > was actually designed this way then that is simply what it is. A true 6 > LUT has 64 memory cells and the associated logic, and two of these seems > a bit excessive and would not require any other logic or muxes at all. > Combining existing 4 LUTs to deliver some of the possible terms of a 6 > LUT is a completely different matter. > > Regardless, it is enjoyable to hear about any radical or innovative new > architecture, as there are so many that now dot the landscape as dead > skeletons of past FPGAs. > > Austin
Reply by ●February 26, 20042004-02-26
Kenneth, We noted that, and it is probably absolutely true. That would yield the same results that we already achieve with our present architecture because a 30% improvement is what is expected (and delivered) by the Virtex LUTs and mux wiring. I grant that they have now achieved parity in LUT usage with our two year old product. They have even improved its speed performance over their St1 by quite a bit, too. Good news for Altera customers. Austin Kenneth Land wrote:> Austin, > > I agree that performance claims will have to wait, but Jesse Kempa posted > the LE results for a Nios softcore on Stratix I vs. II. The numbers showed > just north of 30% fewer LE's used. > > Perhaps you (or someone else) could get your hands on an early version of > Quartus II v4 and build some of your own designs and see for yourself. I'm > sure everyone here would be interested in the results. Maybe someone from > Altera would be willing to do it for you. > > It would be best for someone to use real world designs that they already > have ported to both X and A. > > Ken > > "austin" <austin@xilinx.com> wrote in message > news:c1jt6i$72u1@cliff.xsj.xilinx.com... > >>Michael, >> >>Thank you very much. I have read all of the publicly available >>materials, and am still puzzled by the claims. >> >>Any claims of remarkable efficiency, you may understand, I am quite >>leary of. For example, if the claim of a St2 50% speed improvement is >>really true, then our demonstrated 40% speed improvement on average in >>the i6.2 release makes St2 only 10% faster than our 2 year old V2 >>Pro.....lowest speed grade. So leaving marketing to those who enjoy it, >>I will forego any claims of performance, and just ask about architecture. >> >>I was unclear on just how a ALM is any different from drawing the box >>differently around the components. I am still puzzled, but the block >>diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it >>was actually designed this way then that is simply what it is. A true 6 >>LUT has 64 memory cells and the associated logic, and two of these seems >>a bit excessive and would not require any other logic or muxes at all. >> Combining existing 4 LUTs to deliver some of the possible terms of a 6 >>LUT is a completely different matter. >> >>Regardless, it is enjoyable to hear about any radical or innovative new >>architecture, as there are so many that now dot the landscape as dead >>skeletons of past FPGAs. >> >>Austin > > >
Reply by ●February 26, 20042004-02-26
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<T9d%b.28459$ws.3202154@news02.tsnz.net>...> Michael, > Since you popped your head over the parapet... :) > > What's the story on MAX II Devices ?. There was glossary, timing > and lib files gradually appearing, and suddenly the Altera > web is cleansed and it's like MAX II is now 'off the radar' ?. > Would seem to indicate some problems..... > > -jgHi Jim: Rest assured there are no problems. The www.altera.com site was refreshed; what you are experiencing is "housecleaning" on the site. MAX II data, lib files and documentation will be posted on altera.com when the product is launched - stay tuned. Luanne Schirrmeister -Altera
Reply by ●February 26, 20042004-02-26
Memories of PREP, theidealistic but futile attempt at standardized benchmarks... I really do not like the marketing twist that this thread is taking. Xilinx had extra muxes for many years, Altera counters with more LUT bits, Xilinx explains that Altera shares LUT inputs and has congested routing,... and the spin goes on. In reality its a synthesis and routing software issue. I bet Altera can cook up an application where their LUTs look terrific, and Xilinx can conjure an application where the limited access just chokes the Altera LUTs. And who would be wiser ? Don't expect "gentleman-like" behavior from marketing, the stakes are too high. But let's at least keep this newsgroup somewhat gentleman-like... :-) Peter Alfke ============== Kenneth Land wrote:> > Austin, > > I agree that performance claims will have to wait, but Jesse Kempa posted > the LE results for a Nios softcore on Stratix I vs. II. The numbers showed > just north of 30% fewer LE's used. > > Perhaps you (or someone else) could get your hands on an early version of > Quartus II v4 and build some of your own designs and see for yourself. I'm > sure everyone here would be interested in the results. Maybe someone from > Altera would be willing to do it for you. > > It would be best for someone to use real world designs that they already > have ported to both X and A. > > Ken > > "austin" <austin@xilinx.com> wrote in message > news:c1jt6i$72u1@cliff.xsj.xilinx.com... > > Michael, > > > > Thank you very much. I have read all of the publicly available > > materials, and am still puzzled by the claims. > > > > Any claims of remarkable efficiency, you may understand, I am quite > > leary of. For example, if the claim of a St2 50% speed improvement is > > really true, then our demonstrated 40% speed improvement on average in > > the i6.2 release makes St2 only 10% faster than our 2 year old V2 > > Pro.....lowest speed grade. So leaving marketing to those who enjoy it, > > I will forego any claims of performance, and just ask about architecture. > > > > I was unclear on just how a ALM is any different from drawing the box > > differently around the components. I am still puzzled, but the block > > diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it > > was actually designed this way then that is simply what it is. A true 6 > > LUT has 64 memory cells and the associated logic, and two of these seems > > a bit excessive and would not require any other logic or muxes at all. > > Combining existing 4 LUTs to deliver some of the possible terms of a 6 > > LUT is a completely different matter. > > > > Regardless, it is enjoyable to hear about any radical or innovative new > > architecture, as there are so many that now dot the landscape as dead > > skeletons of past FPGAs. > > > > Austin
Reply by ●February 26, 20042004-02-26
In article <103s244a4ugb899@news.supernews.com>, Kenneth Land <kland1@neuralog1.com1> wrote:>Austin, > >I agree that performance claims will have to wait, but Jesse Kempa posted >the LE results for a Nios softcore on Stratix I vs. II. The numbers showed >just north of 30% fewer LE's used.Considering the impressive design mapping required in the NIOS 2 (the FPGA talk on the subject was VERY-cool), how much redesign was done/needed for Stratix II? Or is this Nios 1.1? -- Nicholas C. Weaver nweaver@cs.berkeley.edu
