Help to SImulate Uart TX

I'm using the following code. I've managed to make it work on my fpga
before. but when I try to simulate on my modelsim, it seems that it
never gets into the statemachine.

I've configured the settings for a 50Mhz clock...also set the config
for model sim to be 10ns 10ns for clock high and low.

How should I go about simulating this?



------------------------------------------------------------------------------
--
-- Engineer: Wojciech Powiertowski
--
-- Module Name: transmitter
-- Project Name: UART
-- Description: A VHDL UART controller
--
-- Comments:
--   If your clkFreq or baudRate values are different than you should
--   calculate proper: phase accumulator width and proper tuning word
with
--   the following equations:
--     phaseAccWidth = round(log2((clkFreq/(baudRate))^2))
--     phaseAccTuning = round(baudRate*2^(phaseAccWidth+1)/clkFreq)
--
-- Example:
--   clkFreq = 100000000       -- 100MHz
--   baudRate = 115200         -- 115.2kHz
--   phaseAccWidth = 19.5233   -- round it up to 20
--   phaseAccTuning = 2415.9   -- round it up to 2416
--
-- generated baud will have frequency of 115199.99 which is only
-- 0.000005% different than ideal baud rate of 115200
--
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity transmitter is
  port(
    clk      : in std_logic;
    startTxD : in std_logic;
    reset    : in std_logic;
    dataTxD  : in std_logic_vector (7 downto 0);
    TxD      : out std_logic;
	 showtick : out std_logic;
    busyTxD  : out std_logic
  );
end transmitter;

architecture TxD_arch of transmitter is
  -- phase accumulator constants and core - see details on top of the
file !!!
  constant phaseAccWidth  : integer := 25;
  constant phaseAccTuning : integer := 12885;
  signal phaseAcc         : std_logic_vector (phaseAccWidth downto 0);

  -- signals in design
  signal dataBuffer : std_logic_vector (7 downto 0);
  signal baudTick   : std_logic;
  signal state      : integer range 0 to 15;
begin

 -- baud generator based on phase accumulator
  baudTickGen : process (clk) is begin
    if(rising_edge(clk))then
      phaseAcc <= phaseAcc + phaseAccTuning;
    end if;
  end process baudTickGen;
  -- MSB of phase accumulator generates the proper baud rate
  baudTick <= phaseAcc(phaseAccWidth);


  -- transmitter: 8 bits of data, no parity control, 1 stop bit
  transmitter : process (baudTick) is begin


    if(rising_edge(baudTick))then
	showtick <='1';
      if(reset = '1')then
        state <= 0;
        dataBuffer <= (others => '0');
      else
        if(state = 0 and startTxD = '0')then
          busyTxD <= '0';
          TxD <= '1';
        elsif(state = 0 and startTxD = '1')then
          TxD <= '0';
          dataBuffer <= dataTxD;
          busyTxD <= '1';
          state <= state + 1;
        elsif(state > 0 and state < 9)then
          busyTxD <= '1';
          TxD <= dataBuffer(state-1);
          state <= state + 1;
        elsif(state = 9)then
          TxD <= '1';
          busyTxD <= '1';
          state <= 0;
        end if;
      end if;


	 end if;
  end process;

end TxD_arch;

"Zhane" <me75@hotmail.com> wrote in message 
news:ae6c34d6-5951-4523-a905-ab06b5b21333@j22g2000hsf.googlegroups.com...
> I'm using the following code. I've managed to make it work on my fpga
> before. but when I try to simulate on my modelsim, it seems that it
> never gets into the statemachine.
>

'Never gets into the statemachine'....is that supposed to mean something? 
(Hint:  It doesn't)

> I've configured the settings for a 50Mhz clock...also set the config
> for model sim to be 10ns 10ns for clock high and low.
>
> How should I go about simulating this?
>

In a word, 'debug'.

Put some waveforms up to view, step through the code, look at the signals, 
however it is that works best for you.  It's your design and testbench, it's 
up to you to figure out what the problem is.  Debugging by newsgroup is 
hardly worth the effort.

KJ 

Zhane wrote:
> I'm using the following code. I've managed to make it work on my fpga
> before. but when I try to simulate on my modelsim, it seems that it
> never gets into the statemachine.

Maybe rising_edge(baudTick) isn't happening.
Have a look at that wave.
A better design would use clk here
and make baudTick a clock enable.

> I've configured the settings for a 50Mhz clock...also set the config
> for model sim to be 10ns 10ns for clock high and low.

What settings?
I would write my own sim clock process.

> How should I go about simulating this?

I would buy a quartus license to get their oem modelsim.

          -- Mike Treseler

On Jul 6, 11:44=A0pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "Zhane" <m...@hotmail.com> wrote in message
>
> news:ae6c34d6-5951-4523-a905-ab06b5b21333@j22g2000hsf.googlegroups.com...
>
> > I'm using the following code. I've managed to make it work on my fpga
> > before. but when I try to simulate on my modelsim, it seems that it
> > never gets into the statemachine.
>
> 'Never gets into the statemachine'....is that supposed to mean something?
> (Hint: =A0It doesn't)
>
> > I've configured the settings for a 50Mhz clock...also set the config
> > for model sim to be 10ns 10ns for clock high and low.
>
> > How should I go about simulating this?
>
> In a word, 'debug'.
>
> Put some waveforms up to view, step through the code, look at the signals=
,
> however it is that works best for you. =A0It's your design and testbench,=
 it's
> up to you to figure out what the problem is. =A0Debugging by newsgroup is
> hardly worth the effort.
>
> KJ

I did
the baudtick does changes, but it doesnt get into the

  if(rising_edge(baudTick))then
        showtick <=3D'1';

section. I've no idea why it happens though..since baudtick changes..
there should be a rising edge

On Jul 7, 12:30=A0am, Mike Treseler <mtrese...@gmail.com> wrote:
> Zhane wrote:
> > I'm using the following code. I've managed to make it work on my fpga
> > before. but when I try to simulate on my modelsim, it seems that it
> > never gets into the statemachine.
>
> Maybe rising_edge(baudTick) isn't happening.
> Have a look at that wave.
> A better design would use clk here
> and make baudTick a clock enable.
>
> > I've configured the settings for a 50Mhz clock...also set the config
> > for model sim to be 10ns 10ns for clock high and low.
>
> What settings?
> I would write my own sim clock process.
>
> > How should I go about simulating this?
>
> I would buy a quartus license to get their oem modelsim.
>
> =A0 =A0 =A0 =A0 =A0 -- Mike Treseler

I changed the settings of the baudgen to match my 9600bps and my 50Mhz
clock.

I'm noob, so trying to save some effort from recoding by using this
code which I found somewhere ~_~

it did work when I try on the actual fpga...

Zhane wrote:

> I've no idea why it happens though..since baudtick changes..
> there should be a rising edge

Does the testbench wait for 2*12885 clk cycles per 'tick'
Does the testbench drive reset back low?
Good luck.

  -- Mike Treseler

PS:
Might want to reset showtick.
Might want to strobify the MSB and sync up both counters to clk.

On Jul 7, 9:31=A0am, Mike Treseler <mike_trese...@comcast.net> wrote:
> Zhane wrote:
> > I've no idea why it happens though..since baudtick changes..
> > there should be a rising edge
>
> Does the testbench wait for 2*12885 clk cycles per 'tick'
> Does the testbench drive reset back low?
> Good luck.
>
> =A0 -- Mike Treseler
>
> PS:
> Might want to reset showtick.
> Might want to strobify the MSB and sync up both counters to clk.

hmm
sorry ... i dont understand what you mean  by ..
> Does the testbench wait for 2*12885 clk cycles per 'tick'
> Might want to strobify the MSB and sync up both counters to clk.

=3D_=3D!!
i only put my reset up for 1 cycle only..the remaining are all low

Zhane wrote:

> I'm noob, so trying to save some effort from recoding by using this
> code which I found somewhere ~_~

If you want to understand it well enough to test it,
read up on direct digital synthesis.

> it did work when I try on the actual fpga...

Good luck.

     -- Mike Treseler

On 8 Lip, 00:46, Mike Treseler <mike_trese...@comcast.net> wrote:
> Zhane wrote:
> > I'm noob, so trying to save some effort from recoding by using this
> > code which I found somewhere ~_~
>
> If you want to understand it well enough to test it,
> read up on direct digital synthesis.
>
> > it did work when I try on the actual fpga...
>
> Good luck.
>
>      -- Mike Treseler

Let me give some suggestions (since I am the author of the code), for
simulation purposes put somewhere
baudTick <= clk;
and omit the phase accumulator

Good luck, oh and if you have any other questions simply write an e-
mail or something since I don't usually check discussion groups.

>A better design would use clk here
>and make baudTick a clock enable.

@ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
phase accumulator works, trust me it is ok the way it is.