Help Needed - LPC Bus Interface

I've problem with my codes.

I'm trying to make a LPC Bus interface with my Spartan 3E to tap the
bus traffic coming from keypresses.

I'm using the LCLK from the bus and the FPGA 50Mhz clock for my
processes. I'm using those expansion connectors to probe the bus,
storing it into a 2-clock FIFO, and a uart which reads from the FIFO
and send it to the PC

I've simulated it on my modelsim and it come out as desired, but when
I try out on the actual thing...the uart data is weird.

I've modified my code to only allow 2 kind of data to be sent out.
"00000000" will be sent out every 13 cycles, while during the 13
cycles it will be the other set of data, "01111111". However the data
I collected doesnt appear to be so.

http://www.savefile.com/files/1655663 << Log file from programming of
FPGA
http://www.savefile.com/files/1655664 << my source codes

Pls help me... I'm at my wits