Hey there, I have asked this question in another forum as well but that forum has gone into the 2nd page and I am not sure how many people would bother going to the next page. Anyways, I am trying to implement IIR filter in VHDL. And for that purpose, I need to use Fixed point arithematic. Now, I came accross the VHDL Fixed point packages available at: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html But I am not sure how to use them? I mean how to compile them? where to copy these downloaded files and then how to compile them? using modelsim? but do I need to start a new ISE project and add all these files, if yes, where to create the project folder? So, basically my question (atm) is that how to use these VHDL packages (a kind of a general question)? I gave a little bit of description about what I am doing coz i thought jus in case.......?? Any comments/suggestions at all are welcome, Thanks very much, Kami

# Using VHDL packages

Started by ●July 12, 2008

Reply by ●July 12, 20082008-07-12

On 7=D4=C213=C8=D5, =C9=CF=CE=E77=CA=B125=B7=D6, "kami" <kamran.wad...@yaho= o.co.uk> wrote:> Hey there, > I have asked this question in another forum as well but that forum has > gone into the 2nd page and I am not sure how many people would bother goi=ng> to the next page. > > Anyways, I am trying to implement IIR filter in VHDL. And for that > purpose, I need to use Fixed point arithematic. > > Now, I came accross the VHDL Fixed point packages available at: > > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html > > But I am not sure how to use them? I mean how to compile them? where to > copy these downloaded files and then how to compile them? using modelsim? > but do I need to start a new ISE project and add all these files, if yes, > where to create the project folder? > > So, basically my question (atm) is that how to use these VHDL packages (a > kind of a general question)? > > I gave a little bit of description about what I am doing coz i thought ju=s> in case.......?? > > Any comments/suggestions at all are welcome, > Thanks very much, > Kamiif you use modelsim, just vcom the pkg file first then your other design files I think is just fine.

Reply by ●July 31, 20082008-07-31

Hi there, I already have the fixed point values for the integers and as they're just 5 coefficients, I have just taken them as constants. Do you think it is alright? Well, then I am giving input(16-bit {1 sign bit and 15 fractional bits}) from the switches and buttons on the Spartan-3 board. As there are just 4 1-bit push buttons and an 8-bit switch (12-bits altogether, and then I am keeping 4 bits constant). Then the output is also 16-bit which includes 1 sign bit, 4 integer bits and 11 fractional bits. Now, I have used the 7-segment display to show the output in such a way that the leftmost digit is showing the hex value of 4 integer bits, and then a dot to show decimal point and then the next 3 digits for fractional part but as there are 11-bits in fractional part, so, I have padded a zero at the end of fractional part just to make it a 4-bit value for the hex-decoder. And then I am using the last dp (dot/decimal point on 7-seg display to indicate the sign of the number). So, I am only giving input from the board and getting the output and not using any RAM/ROM or multiplier blocks, I have only used constants and the operators ('+', '-', '*') and left it all to the VHDL to do all the intermediate arithmetic and use the hardware components as required, will it be fine? Do you think it is a good design? Now, I was wondering what will be the best option if I wanted to demonstrate the filter operation more clearly. I mean these are just numbers that I am showing on the 7-seg display. But if I want to give a sinusoidal input and get a filtered waveform at the output. 1)I have got the code for vhdl sine generator. 2)Showing the ouput on the oscilloscope? it sounds a bit tedious. 3)Do you think interfacing a microphone and speaker would work for this design (and for Spartan-3)? 4)or any other application/test case you would suggest for IIR filter on FPGA? Thanks very much for your help. Regards, Kami>> Kami > >if you use modelsim, just vcom the pkg file first then your other >design files I think is just fine. >

Reply by ●July 31, 20082008-07-31

kami wrote:> I already have the fixed point values for the integers and as they're just > 5 coefficients, I have just taken them as constants. Do you think it is > alright?If I were designing a IIR filter I would start in the dsp domain and work my way down. See: http://www.kxcad.net/cae_MATLAB/toolbox/hdlfilter/a1075521372b1.html I would focus on getting some sample data. Without expected values for my filter, what do I have to demonstrate?> So, I am only giving input from the board and getting the output and not > using any RAM/ROM or multiplier blocks, I have only used constants and the > operators ('+', '-', '*') and left it all to the VHDL to do all the > intermediate arithmetic and use the hardware components as required, will > it be fine?+ and - is fine, * will be a problem without using the dsp blocks.> Do you think it is a good design?If it works, it will be good. Keep it simple. -- Mike Treseler

Reply by ●July 31, 20082008-07-31

Hi Mike, Thanks very much for your reply. Please see my answers (and answers with questions) below:>If I were designing a IIR filter I would start in >the dsp domain and work my way down. See: >http://www.kxcad.net/cae_MATLAB/toolbox/hdlfilter/a1075521372b1.htmlYes, that's exactly what I have done. I think I didn't explain that much but yes, that's what I've done. Infact, I should say, exactly the same process as described in the link you've posted. I developed a SIMULINK model and performed analysis. Then quantized the filter to make it fixed-point and then generated HDL code and test-bench. But then I only used the generated HDL code of filter and wrote another VHDL code for testing it on FPGA and got the results as mentioned in my last post. So, the logic for the filter is basically from the HDL code generated by MATLAB FDA tool.>I would focus on getting some sample data. >Without expected values for my filter, >what do I have to demonstrate?Sorry, I couldn't quite get your point, do you mean the input that I am giving? But it's being assigned through the buttons and switches which can be changed. Or do you mean giving a real-time signal input? like speech or any anlaogue input?>+ and - is fine, * will be a problem without using the dsp blocks.Well, not really I think, because I could see in the synthesis report that 3 MULT_18x18 blocks {Multiplier blocks} are being used. So, that means the code is invoking those blocks by itself. I mean the '*' operator is doing the bit.>> Do you think it is a good design? > >If it works, it will be good. >Keep it simple.Well as I have mentioned earlier on that it's giving the 16-bit binary output that I could show on the 7-segment display in hexadecimal format, I can say it sounds good. But I want to make it look like an IIR filter. I mean the algorithm is working (at least, I think so) now, it's just the front end which can make it speak that I am an IIR filter. Any suggestions/comments please? Thanks very much for your time and help, Much Appreciated, Kami