Hey all, I have a Xilinx Spartan-3E starter board, and I'm implementing a MicroBlaze processor on the FPGA. I would also like to use the LCD which is on board, and I have already developed a hardware module that takes care of initialization and printing to the LCD. The interface is shown below: entity LCD_top is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; din : in STD_LOGIC_VECTOR (7 downto 0); din_ready : in STD_LOGIC; busy : out STD_LOGIC; LCD_D : out STD_LOGIC_VECTOR (11 downto 8); LCD_E : out STD_LOGIC; LCD_RS : out STD_LOGIC; LCD_RW : out STD_LOGIC ); end LCD_top; I really would like to instantiate this module along with the processor core. My question is this - how would I go about interfacing this with the MicroBlaze processor internal to the FPGA? What I would like to do is define a GPIO port on the processor to connect to the din, din_ready and busy lines of the LCD module, but I keep getting the following error: ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD \system.mhs line 150 - connection is not connected to an external port! MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require that the port be connected directly to an external port. Is there any way to work around this? I realize I could just connect the LCD to the GPIO directly and write software drivers, but I'm trying to avoid that because I already have the hardware module in place and working smoothly. It will also be nice to have this separate module so that it does the work of printing to the LCD, and the processor itself can stay busy with other more important jobs. Also, is there an easier way to add another hardware module without manually editing the generated VHDL files for the core? I'm not sure if you can do that within Platform Studio. Any advice would be much appreciated, thanks! Ray
Additional Hardware Module with Xilinx MicroBlaze Processor
Started by ●July 18, 2008
Reply by ●July 18, 20082008-07-18
On Jul 18, 1:21=A0pm, "Ray D." <ray.delvecc...@gmail.com> wrote:> Hey all, > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > MicroBlaze processor on the FPGA. =A0I would also like to use the LCD > which is on board, and I have already developed a hardware module that > takes care of initialization and printing to the LCD. =A0The interface > is shown below: > > entity LCD_top is > =A0 =A0 Port ( > =A0 =A0 =A0 =A0 =A0 =A0clk : in =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0reset : in =A0STD_LOGIC; > > =A0 =A0 =A0 =A0 =A0 =A0din : in STD_LOGIC_VECTOR (7 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0din_ready : in STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0busy : out STD_LOGIC; > > =A0 =A0 =A0 =A0 =A0 =A0LCD_D : out =A0STD_LOGIC_VECTOR (11 downto 8); > =A0 =A0 =A0 =A0 =A0 =A0LCD_E : out =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0LCD_RS : out =A0STD_LOGIC; > =A0 =A0 =A0 =A0 =A0 =A0LCD_RW : out =A0STD_LOGIC > > =A0 =A0 =A0 =A0 ); > end LCD_top; > > I really would like to instantiate this module along with the > processor core. =A0My question is this - how would I go about > interfacing this with the MicroBlaze processor internal to the FPGA? > What I would like to do is define a GPIO port on the processor to > connect to the din, din_ready and busy lines of the LCD module, but I > keep getting the following error: > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > =A0 =A0CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > \system.mhs line 150 > =A0 =A0- connection is not connected to an external port! > =A0 =A0MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE requir=e> that the port > =A0 =A0be connected directly to an external port. > > Is there any way to work around this? =A0I realize I could just connect > the LCD to the GPIO directly and write software drivers, but I'm > trying to avoid that because I already have the hardware module in > place and working smoothly. =A0It will also be nice to have this > separate module so that it does the work of printing to the LCD, and > the processor itself can stay busy with other more important jobs. > > Also, is there an easier way to add another hardware module without > manually editing the generated VHDL files for the core? =A0I'm not sure > if you can do that within Platform Studio. > > Any advice would be much appreciated, thanks! > > RayThe "IOB_STATE=3DBUF|REG" part of the error message means that the GPIO core is instantiating IOB primitives in its code instead of letting Platgen infer them. That means that this core will not be happy unless those ports are made external and go to FPGA pins. I would suggest creating a simple OPB interface to your core. The OPB bus is simple, and creating a slave interface to what you show above would not be hard. The OPB is documented in $EDK/third_party/doc/OpbBus.pdf. That might be part of the IBM CoreConnect Bus Functional Model tool kit. If it is, you just register for the tool kit on the Xilinx web site to get access to it. For you second question, did you package your LCD code as an EDK Pcore? If you do that, you can add the core through the GUI. Regards, John McCaskill www.FasterTechnology.com
Reply by ●July 19, 20082008-07-19
On Fri, 18 Jul 2008 13:21:54 -0700 (PDT), "Ray D." <ray.delvecchio@gmail.com> wrote:>Hey all, > >I have a Xilinx Spartan-3E starter board, and I'm implementing a >MicroBlaze processor on the FPGA. I would also like to use the LCD >which is on board, and I have already developed a hardware module that >takes care of initialization and printing to the LCD. The interface >is shown below: > >entity LCD_top is > Port ( > clk : in STD_LOGIC; > reset : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (7 downto 0); > din_ready : in STD_LOGIC; > busy : out STD_LOGIC; > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > LCD_E : out STD_LOGIC; > LCD_RS : out STD_LOGIC; > LCD_RW : out STD_LOGIC > > ); >end LCD_top; > >I really would like to instantiate this module along with the >processor core. My question is this - how would I go about >interfacing this with the MicroBlaze processor internal to the FPGA?The problem is that EDK basically wants all EDK blocks in its design, and assumes that anything you want to do can be done with EDK blocks, such as GPIO. I agree with John that you probably want an OPB bus interface to the LCD device; the question is the easiest way to create one. The OPB bus looks complex, if you take all the optional features into account. John's view is that it isn't, but if you need DMA or other special features it may get tricky. Using DMA, I have seen bugs in the Xilinx-supplied cores (in the EDK 7.1 era) which either shows it's complex, or suggests you roll your own in place of the vendor cores! If you don't want to delve straight into OPB, look at the "OPB IPIF" module which is a starting point for your own OPB core. What I did with this was to add whatever I/O signals I wanted (e.g. to talk to your LCD interface) to the IPIF top level, and simply connect them up to the IPIF interface internally, in the section indicated for user logic. I did it this way because the EDK project was a small bolt-on to a large project. It would be more straightforward to instantiate the LCD controller in the IPIF user logic area; and thus wrap it as an EDK block. I'm not recommending this as a better option than rolling your own OPB core, but it's an alternative worth looking at; possibly simpler for a first EDK project. - Brian
Reply by ●July 21, 20082008-07-21
Hi, Depending a little on how your busy signals work, you might just hook up your module to the FSL interface on MicroBlaze. Your busy signal needs be high when it can't accept a new word even when there is no attempt to write to the module. MicroBlaze will also just do one cycle write so your module needs to accept a new word in one clock cycle when busy is low. Connect: din(7 downto 0) -> FSL0_M_Data(24 to 31) din_ready -> FSL0_M_Write busy -> FSL0_M_Full You need to enable FSL Interfaces to MicroBlaze with the parameter C_FSL_LINKS (set it to 1) You can write to the fsl interface with the function putfslx, you can read more about this function in the document "OS and Libraries Document Collection". G�ran "Ray D." <ray.delvecchio@gmail.com> wrote in message news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com...> Hey all, > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > MicroBlaze processor on the FPGA. I would also like to use the LCD > which is on board, and I have already developed a hardware module that > takes care of initialization and printing to the LCD. The interface > is shown below: > > entity LCD_top is > Port ( > clk : in STD_LOGIC; > reset : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (7 downto 0); > din_ready : in STD_LOGIC; > busy : out STD_LOGIC; > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > LCD_E : out STD_LOGIC; > LCD_RS : out STD_LOGIC; > LCD_RW : out STD_LOGIC > > ); > end LCD_top; > > I really would like to instantiate this module along with the > processor core. My question is this - how would I go about > interfacing this with the MicroBlaze processor internal to the FPGA? > What I would like to do is define a GPIO port on the processor to > connect to the din, din_ready and busy lines of the LCD module, but I > keep getting the following error: > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > \system.mhs line 150 > - connection is not connected to an external port! > MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require > that the port > be connected directly to an external port. > > Is there any way to work around this? I realize I could just connect > the LCD to the GPIO directly and write software drivers, but I'm > trying to avoid that because I already have the hardware module in > place and working smoothly. It will also be nice to have this > separate module so that it does the work of printing to the LCD, and > the processor itself can stay busy with other more important jobs. > > Also, is there an easier way to add another hardware module without > manually editing the generated VHDL files for the core? I'm not sure > if you can do that within Platform Studio. > > Any advice would be much appreciated, thanks! > > Ray
Reply by ●July 21, 20082008-07-21
On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote:> Hi, > > Depending a little on how your busy signals work, you might just hook up > your module to the FSL interface on MicroBlaze. > Your busy signal needs be high when it can't accept a new word even when > there is no attempt to write to the module. > MicroBlaze will also just do one cycle write so your module needs to acce=pt> a new word in one clock cycle when busy is low. > > Connect: > din(7 downto 0) -> FSL0_M_Data(24 to 31) > din_ready -> FSL0_M_Write > busy -> FSL0_M_Full > > You need to enable FSL Interfaces to MicroBlaze with the parameter > C_FSL_LINKS (set it to 1) > You can write to the fsl interface with the function putfslx, you can rea=d> more about this function in the document "OS and Libraries Document > Collection". > > G=F6ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com... > > > Hey all, > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > MicroBlaze processor on the FPGA. I would also like to use the LCD > > which is on board, and I have already developed a hardware module that > > takes care of initialization and printing to the LCD. The interface > > is shown below: > > > entity LCD_top is > > Port ( > > clk : in STD_LOGIC; > > reset : in STD_LOGIC; > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > din_ready : in STD_LOGIC; > > busy : out STD_LOGIC; > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > LCD_E : out STD_LOGIC; > > LCD_RS : out STD_LOGIC; > > LCD_RW : out STD_LOGIC > > > ); > > end LCD_top; > > > I really would like to instantiate this module along with the > > processor core. My question is this - how would I go about > > interfacing this with the MicroBlaze processor internal to the FPGA? > > What I would like to do is define a GPIO port on the processor to > > connect to the din, din_ready and busy lines of the LCD module, but I > > keep getting the following error: > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > \system.mhs line 150 > > - connection is not connected to an external port! > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE require > > that the port > > be connected directly to an external port. > > > Is there any way to work around this? I realize I could just connect > > the LCD to the GPIO directly and write software drivers, but I'm > > trying to avoid that because I already have the hardware module in > > place and working smoothly. It will also be nice to have this > > separate module so that it does the work of printing to the LCD, and > > the processor itself can stay busy with other more important jobs. > > > Also, is there an easier way to add another hardware module without > > manually editing the generated VHDL files for the core? I'm not sure > > if you can do that within Platform Studio. > > > Any advice would be much appreciated, thanks! > > > RayThat is how the module works so I'll have to try some of these options! The busy signal is set high the entire time data is being written to the LCD. Originally I had a module "program.vhd" that controlled the LCD module along with a keyboard module that we we had in place for user input. Within program.vhd, I implement a state machine and check if the busy signal is high before writing to the LCD. If busy =3D 0, then I set din_ready high and set the 8-bits of data. This is buffered within the LCD module and you only need to hold din_ready for a single cycle to write to the LCD. The LCD is connected over a 4-bit interface to the FPGA and this is taken care of within the LCD module. When the writing operation begins busy is set to '1' until complete. Ray
Reply by ●July 22, 20082008-07-22
Hi, Then it should be a direct match for the FSL interface. If MicroBlaze executes a 'put' instruction , it will not write until the FSL_M_Full flag is '0' and when it write it will set the FSL_M Write high for one clock cycle. MicroBlaze have plenty of options for the FSL instructions, you can get all about them in the reference manual. G�ran "Ray D." <ray.delvecchio@gmail.com> wrote in message news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com... On Jul 21, 2:36 am, "G�ran Bilski" <goran.bil...@xilinx.com> wrote:> Hi, > > Depending a little on how your busy signals work, you might just hook up > your module to the FSL interface on MicroBlaze. > Your busy signal needs be high when it can't accept a new word even when > there is no attempt to write to the module. > MicroBlaze will also just do one cycle write so your module needs to > accept > a new word in one clock cycle when busy is low. > > Connect: > din(7 downto 0) -> FSL0_M_Data(24 to 31) > din_ready -> FSL0_M_Write > busy -> FSL0_M_Full > > You need to enable FSL Interfaces to MicroBlaze with the parameter > C_FSL_LINKS (set it to 1) > You can write to the fsl interface with the function putfslx, you can read > more about this function in the document "OS and Libraries Document > Collection". > > G�ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com... > > > Hey all, > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > MicroBlaze processor on the FPGA. I would also like to use the LCD > > which is on board, and I have already developed a hardware module that > > takes care of initialization and printing to the LCD. The interface > > is shown below: > > > entity LCD_top is > > Port ( > > clk : in STD_LOGIC; > > reset : in STD_LOGIC; > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > din_ready : in STD_LOGIC; > > busy : out STD_LOGIC; > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > LCD_E : out STD_LOGIC; > > LCD_RS : out STD_LOGIC; > > LCD_RW : out STD_LOGIC > > > ); > > end LCD_top; > > > I really would like to instantiate this module along with the > > processor core. My question is this - how would I go about > > interfacing this with the MicroBlaze processor internal to the FPGA? > > What I would like to do is define a GPIO port on the processor to > > connect to the din, din_ready and busy lines of the LCD module, but I > > keep getting the following error: > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > \system.mhs line 150 > > - connection is not connected to an external port! > > MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require > > that the port > > be connected directly to an external port. > > > Is there any way to work around this? I realize I could just connect > > the LCD to the GPIO directly and write software drivers, but I'm > > trying to avoid that because I already have the hardware module in > > place and working smoothly. It will also be nice to have this > > separate module so that it does the work of printing to the LCD, and > > the processor itself can stay busy with other more important jobs. > > > Also, is there an easier way to add another hardware module without > > manually editing the generated VHDL files for the core? I'm not sure > > if you can do that within Platform Studio. > > > Any advice would be much appreciated, thanks! > > > RayThat is how the module works so I'll have to try some of these options! The busy signal is set high the entire time data is being written to the LCD. Originally I had a module "program.vhd" that controlled the LCD module along with a keyboard module that we we had in place for user input. Within program.vhd, I implement a state machine and check if the busy signal is high before writing to the LCD. If busy = 0, then I set din_ready high and set the 8-bits of data. This is buffered within the LCD module and you only need to hold din_ready for a single cycle to write to the LCD. The LCD is connected over a 4-bit interface to the FPGA and this is taken care of within the LCD module. When the writing operation begins busy is set to '1' until complete. Ray
Reply by ●July 23, 20082008-07-23
On Jul 22, 2:34 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote:> Hi, > > Then it should be a direct match for the FSL interface. > If MicroBlaze executes a 'put' instruction , it will not write until the > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write high > for one clock cycle. > MicroBlaze have plenty of options for the FSL instructions, you can get a=ll> about them in the reference manual. > > G=F6ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com... > On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > Depending a little on how your busy signals work, you might just hook u=p> > your module to the FSL interface on MicroBlaze. > > Your busy signal needs be high when it can't accept a new word even whe=n> > there is no attempt to write to the module. > > MicroBlaze will also just do one cycle write so your module needs to > > accept > > a new word in one clock cycle when busy is low. > > > Connect: > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > din_ready -> FSL0_M_Write > > busy -> FSL0_M_Full > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > C_FSL_LINKS (set it to 1) > > You can write to the fsl interface with the function putfslx, you can r=ead> > more about this function in the document "OS and Libraries Document > > Collection". > > > G=F6ran > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com..=.> > > > Hey all, > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > MicroBlaze processor on the FPGA. I would also like to use the LCD > > > which is on board, and I have already developed a hardware module tha=t> > > takes care of initialization and printing to the LCD. The interface > > > is shown below: > > > > entity LCD_top is > > > Port ( > > > clk : in STD_LOGIC; > > > reset : in STD_LOGIC; > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > din_ready : in STD_LOGIC; > > > busy : out STD_LOGIC; > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > LCD_E : out STD_LOGIC; > > > LCD_RS : out STD_LOGIC; > > > LCD_RW : out STD_LOGIC > > > > ); > > > end LCD_top; > > > > I really would like to instantiate this module along with the > > > processor core. My question is this - how would I go about > > > interfacing this with the MicroBlaze processor internal to the FPGA? > > > What I would like to do is define a GPIO port on the processor to > > > connect to the din, din_ready and busy lines of the LCD module, but I > > > keep getting the following error: > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > \system.mhs line 150 > > > - connection is not connected to an external port! > > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE require > > > that the port > > > be connected directly to an external port. > > > > Is there any way to work around this? I realize I could just connect > > > the LCD to the GPIO directly and write software drivers, but I'm > > > trying to avoid that because I already have the hardware module in > > > place and working smoothly. It will also be nice to have this > > > separate module so that it does the work of printing to the LCD, and > > > the processor itself can stay busy with other more important jobs. > > > > Also, is there an easier way to add another hardware module without > > > manually editing the generated VHDL files for the core? I'm not sure > > > if you can do that within Platform Studio. > > > > Any advice would be much appreciated, thanks! > > > > Ray > > That is how the module works so I'll have to try some of these > options! The busy signal is set high the entire time data is being > written to the LCD. Originally I had a module "program.vhd" that > controlled the LCD module along with a keyboard module that we we had > in place for user input. Within program.vhd, I implement a state > machine and check if the busy signal is high before writing to the > LCD. If busy =3D 0, then I set din_ready high and set the 8-bits of > data. This is buffered within the LCD module and you only need to > hold din_ready for a single cycle to write to the LCD. The LCD is > connected over a 4-bit interface to the FPGA and this is taken care of > within the LCD module. When the writing operation begins busy is set > to '1' until complete. > > RayOK - I'm new to using the EDK and am having trouble implementing this with the FSL bus. I have a few questions: 1) When I create a custom peripheral, it generates an HDL wrapper - Do I simply edit this wrapper by instantiating my LCD_top module as a component within the top level design? 2) Should I check the box "Generate template driver files to help you implement software interface", or will the provided functions to read and write to the FSL bus suffice? 3) Do you know of any good tutorials on how to implement a custom peripheral on the FSL bus? I've come across a few for adding peripherals to the other buses, but most that I have found do not follow through with how to edit the VHDL files and correctly add the peripheral to the system in Platform Studio (they simply tell you go to 'Create/Import Custom Peripheral'). Any help/input is appreciated, thanks! Ray
Reply by ●July 23, 20082008-07-23
On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote:> On Jul 22, 2:34 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > Then it should be a direct match for the FSL interface. > > If MicroBlaze executes a 'put' instruction , it will not write until th=e> > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write hi=gh> > for one clock cycle. > > MicroBlaze have plenty of options for the FSL instructions, you can get=all> > about them in the reference manual. > > > G=F6ran > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com... > > On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > Hi, > > > > Depending a little on how your busy signals work, you might just hook=up> > > your module to the FSL interface on MicroBlaze. > > > Your busy signal needs be high when it can't accept a new word even w=hen> > > there is no attempt to write to the module. > > > MicroBlaze will also just do one cycle write so your module needs to > > > accept > > > a new word in one clock cycle when busy is low. > > > > Connect: > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > din_ready -> FSL0_M_Write > > > busy -> FSL0_M_Full > > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > > C_FSL_LINKS (set it to 1) > > > You can write to the fsl interface with the function putfslx, you can=read> > > more about this function in the document "OS and Libraries Document > > > Collection". > > > > G=F6ran > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com=...> > > > > Hey all, > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > > MicroBlaze processor on the FPGA. I would also like to use the LCD > > > > which is on board, and I have already developed a hardware module t=hat> > > > takes care of initialization and printing to the LCD. The interfac=e> > > > is shown below: > > > > > entity LCD_top is > > > > Port ( > > > > clk : in STD_LOGIC; > > > > reset : in STD_LOGIC; > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > din_ready : in STD_LOGIC; > > > > busy : out STD_LOGIC; > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > LCD_E : out STD_LOGIC; > > > > LCD_RS : out STD_LOGIC; > > > > LCD_RW : out STD_LOGIC > > > > > ); > > > > end LCD_top; > > > > > I really would like to instantiate this module along with the > > > > processor core. My question is this - how would I go about > > > > interfacing this with the MicroBlaze processor internal to the FPGA=?> > > > What I would like to do is define a GPIO port on the processor to > > > > connect to the din, din_ready and busy lines of the LCD module, but=I> > > > keep getting the following error: > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > \system.mhs line 150 > > > > - connection is not connected to an external port! > > > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE requi=re> > > > that the port > > > > be connected directly to an external port. > > > > > Is there any way to work around this? I realize I could just conne=ct> > > > the LCD to the GPIO directly and write software drivers, but I'm > > > > trying to avoid that because I already have the hardware module in > > > > place and working smoothly. It will also be nice to have this > > > > separate module so that it does the work of printing to the LCD, an=d> > > > the processor itself can stay busy with other more important jobs. > > > > > Also, is there an easier way to add another hardware module without > > > > manually editing the generated VHDL files for the core? I'm not su=re> > > > if you can do that within Platform Studio. > > > > > Any advice would be much appreciated, thanks! > > > > > Ray > > > That is how the module works so I'll have to try some of these > > options! The busy signal is set high the entire time data is being > > written to the LCD. Originally I had a module "program.vhd" that > > controlled the LCD module along with a keyboard module that we we had > > in place for user input. Within program.vhd, I implement a state > > machine and check if the busy signal is high before writing to the > > LCD. If busy =3D 0, then I set din_ready high and set the 8-bits of > > data. This is buffered within the LCD module and you only need to > > hold din_ready for a single cycle to write to the LCD. The LCD is > > connected over a 4-bit interface to the FPGA and this is taken care of > > within the LCD module. When the writing operation begins busy is set > > to '1' until complete. > > > Ray > > OK - I'm new to using the EDK and am having trouble implementing this > with the FSL bus. I have a few questions: > > 1) When I create a custom peripheral, it generates an HDL wrapper - Do > I simply edit this wrapper by instantiating my LCD_top module as a > component within the top level design? > > 2) Should I check the box "Generate template driver files to help you > implement software interface", or will the provided functions to read > and write to the FSL bus suffice? > > 3) Do you know of any good tutorials on how to implement a custom > peripheral on the FSL bus? I've come across a few for adding > peripherals to the other buses, but most that I have found do not > follow through with how to edit the VHDL files and correctly add the > peripheral to the system in Platform Studio (they simply tell you go > to 'Create/Import Custom Peripheral'). > > Any help/input is appreciated, thanks! > > RayTwo more things - 1) the four output ports of the LCD module must be connected to the external FPGA pins in order to drive the LCD. What is the best way to go about doing this? Is this something that can be edited within Platform Studio or do I need to manually edit VHDL/UCF files? I'm assuming I will have to add the outputs to the interface shown below. 2) When I choose the master interface for the FSL bus, the ports are defined as follows: -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add or delete. FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- You mention that my din(7 downto 0) port should be connected to the FSL_M_Data port, but the former is an input while the latter is an output. Am I missing something? I tried to define this as a slave interface, but that also yields an error when I try to generate the bitstream. Thanks.
Reply by ●July 24, 20082008-07-24
Hi, You don't need the FSL_bus. You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full, FSL0_M_Write and connect them to your module. If you want to do this in EDK, you will need to create a pcore for your module and manually connect these signal in XPS. You can also make these signal external to the EDK project and connect them in Project Navigator. It's depend on how your design look now. G�ran "Ray D." <ray.delvecchio@gmail.com> wrote in message news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com... On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote:> On Jul 22, 2:34 am, "G�ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > Then it should be a direct match for the FSL interface. > > If MicroBlaze executes a 'put' instruction , it will not write until the > > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write > > high > > for one clock cycle. > > MicroBlaze have plenty of options for the FSL instructions, you can get > > all > > about them in the reference manual. > > > G�ran > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com... > > On Jul 21, 2:36 am, "G�ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > Hi, > > > > Depending a little on how your busy signals work, you might just hook > > > up > > > your module to the FSL interface on MicroBlaze. > > > Your busy signal needs be high when it can't accept a new word even > > > when > > > there is no attempt to write to the module. > > > MicroBlaze will also just do one cycle write so your module needs to > > > accept > > > a new word in one clock cycle when busy is low. > > > > Connect: > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > din_ready -> FSL0_M_Write > > > busy -> FSL0_M_Full > > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > > C_FSL_LINKS (set it to 1) > > > You can write to the fsl interface with the function putfslx, you can > > > read > > > more about this function in the document "OS and Libraries Document > > > Collection". > > > > G�ran > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.com... > > > > > Hey all, > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > > MicroBlaze processor on the FPGA. I would also like to use the LCD > > > > which is on board, and I have already developed a hardware module > > > > that > > > > takes care of initialization and printing to the LCD. The interface > > > > is shown below: > > > > > entity LCD_top is > > > > Port ( > > > > clk : in STD_LOGIC; > > > > reset : in STD_LOGIC; > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > din_ready : in STD_LOGIC; > > > > busy : out STD_LOGIC; > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > LCD_E : out STD_LOGIC; > > > > LCD_RS : out STD_LOGIC; > > > > LCD_RW : out STD_LOGIC > > > > > ); > > > > end LCD_top; > > > > > I really would like to instantiate this module along with the > > > > processor core. My question is this - how would I go about > > > > interfacing this with the MicroBlaze processor internal to the FPGA? > > > > What I would like to do is define a GPIO port on the processor to > > > > connect to the din, din_ready and busy lines of the LCD module, but > > > > I > > > > keep getting the following error: > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > \system.mhs line 150 > > > > - connection is not connected to an external port! > > > > MPD subproperties IOB_STATE=BUF|REG or THREE_STATE=TRUE require > > > > that the port > > > > be connected directly to an external port. > > > > > Is there any way to work around this? I realize I could just > > > > connect > > > > the LCD to the GPIO directly and write software drivers, but I'm > > > > trying to avoid that because I already have the hardware module in > > > > place and working smoothly. It will also be nice to have this > > > > separate module so that it does the work of printing to the LCD, and > > > > the processor itself can stay busy with other more important jobs. > > > > > Also, is there an easier way to add another hardware module without > > > > manually editing the generated VHDL files for the core? I'm not > > > > sure > > > > if you can do that within Platform Studio. > > > > > Any advice would be much appreciated, thanks! > > > > > Ray > > > That is how the module works so I'll have to try some of these > > options! The busy signal is set high the entire time data is being > > written to the LCD. Originally I had a module "program.vhd" that > > controlled the LCD module along with a keyboard module that we we had > > in place for user input. Within program.vhd, I implement a state > > machine and check if the busy signal is high before writing to the > > LCD. If busy = 0, then I set din_ready high and set the 8-bits of > > data. This is buffered within the LCD module and you only need to > > hold din_ready for a single cycle to write to the LCD. The LCD is > > connected over a 4-bit interface to the FPGA and this is taken care of > > within the LCD module. When the writing operation begins busy is set > > to '1' until complete. > > > Ray > > OK - I'm new to using the EDK and am having trouble implementing this > with the FSL bus. I have a few questions: > > 1) When I create a custom peripheral, it generates an HDL wrapper - Do > I simply edit this wrapper by instantiating my LCD_top module as a > component within the top level design? > > 2) Should I check the box "Generate template driver files to help you > implement software interface", or will the provided functions to read > and write to the FSL bus suffice? > > 3) Do you know of any good tutorials on how to implement a custom > peripheral on the FSL bus? I've come across a few for adding > peripherals to the other buses, but most that I have found do not > follow through with how to edit the VHDL files and correctly add the > peripheral to the system in Platform Studio (they simply tell you go > to 'Create/Import Custom Peripheral'). > > Any help/input is appreciated, thanks! > > RayTwo more things - 1) the four output ports of the LCD module must be connected to the external FPGA pins in order to drive the LCD. What is the best way to go about doing this? Is this something that can be edited within Platform Studio or do I need to manually edit VHDL/UCF files? I'm assuming I will have to add the outputs to the interface shown below. 2) When I choose the master interface for the FSL bus, the ports are defined as follows: -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add or delete. FSL_Clk : in std_logic; FSL_Rst : in std_logic; FSL_S_Clk : out std_logic; FSL_S_Read : out std_logic; FSL_S_Data : in std_logic_vector(0 to 31); FSL_S_Control : in std_logic; FSL_S_Exists : in std_logic; FSL_M_Clk : out std_logic; FSL_M_Write : out std_logic; FSL_M_Data : out std_logic_vector(0 to 31); FSL_M_Control : out std_logic; FSL_M_Full : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- You mention that my din(7 downto 0) port should be connected to the FSL_M_Data port, but the former is an input while the latter is an output. Am I missing something? I tried to define this as a slave interface, but that also yields an error when I try to generate the bitstream. Thanks.
Reply by ●July 24, 20082008-07-24
On Jul 24, 2:44 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote:> Hi, > > You don't need the FSL_bus. > You can directly take the MicroBlaze signals FSL0_M_Data, FSL0_M_Full, > FSL0_M_Write and connect them to your module. > If you want to do this in EDK, you will need to create a pcore for your > module and manually connect these signal in XPS. > You can also make these signal external to the EDK project and connect th=em> in Project Navigator. > It's depend on how your design look now. > > G=F6ran > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > news:0b840fac-04c0-41a6-8ca1-99593fe48018@l64g2000hse.googlegroups.com... > On Jul 23, 3:26 pm, "Ray D." <ray.delvecc...@gmail.com> wrote: > > > > > On Jul 22, 2:34 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > Hi, > > > > Then it should be a direct match for the FSL interface. > > > If MicroBlaze executes a 'put' instruction , it will not write until =the> > > FSL_M_Full flag is '0' and when it write it will set the FSL_M Write > > > high > > > for one clock cycle. > > > MicroBlaze have plenty of options for the FSL instructions, you can g=et> > > all > > > about them in the reference manual. > > > > G=F6ran > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > >news:693f947e-929e-49f6-939d-d834e0048121@27g2000hsf.googlegroups.com.=..> > > On Jul 21, 2:36 am, "G=F6ran Bilski" <goran.bil...@xilinx.com> wrote: > > > > > Hi, > > > > > Depending a little on how your busy signals work, you might just ho=ok> > > > up > > > > your module to the FSL interface on MicroBlaze. > > > > Your busy signal needs be high when it can't accept a new word even > > > > when > > > > there is no attempt to write to the module. > > > > MicroBlaze will also just do one cycle write so your module needs t=o> > > > accept > > > > a new word in one clock cycle when busy is low. > > > > > Connect: > > > > din(7 downto 0) -> FSL0_M_Data(24 to 31) > > > > din_ready -> FSL0_M_Write > > > > busy -> FSL0_M_Full > > > > > You need to enable FSL Interfaces to MicroBlaze with the parameter > > > > C_FSL_LINKS (set it to 1) > > > > You can write to the fsl interface with the function putfslx, you c=an> > > > read > > > > more about this function in the document "OS and Libraries Document > > > > Collection". > > > > > G=F6ran > > > > > "Ray D." <ray.delvecc...@gmail.com> wrote in message > > > > >news:276dce6d-c9ed-4937-95ea-e3c86ff3656a@d45g2000hsc.googlegroups.c=om...> > > > > > Hey all, > > > > > > I have a Xilinx Spartan-3E starter board, and I'm implementing a > > > > > MicroBlaze processor on the FPGA. I would also like to use the L=CD> > > > > which is on board, and I have already developed a hardware module > > > > > that > > > > > takes care of initialization and printing to the LCD. The interf=ace> > > > > is shown below: > > > > > > entity LCD_top is > > > > > Port ( > > > > > clk : in STD_LOGIC; > > > > > reset : in STD_LOGIC; > > > > > > din : in STD_LOGIC_VECTOR (7 downto 0); > > > > > din_ready : in STD_LOGIC; > > > > > busy : out STD_LOGIC; > > > > > > LCD_D : out STD_LOGIC_VECTOR (11 downto 8); > > > > > LCD_E : out STD_LOGIC; > > > > > LCD_RS : out STD_LOGIC; > > > > > LCD_RW : out STD_LOGIC > > > > > > ); > > > > > end LCD_top; > > > > > > I really would like to instantiate this module along with the > > > > > processor core. My question is this - how would I go about > > > > > interfacing this with the MicroBlaze processor internal to the FP=GA?> > > > > What I would like to do is define a GPIO port on the processor to > > > > > connect to the din, din_ready and busy lines of the LCD module, b=ut> > > > > I > > > > > keep getting the following error: > > > > > > ERROR:MDT - INST:LCD_data_status_10Bit PORT:GPIO_IO > > > > > CONNECTOR:LCD_data_status_10Bit_GPIO_IO - C:\EDK_Test_LCD > > > > > \system.mhs line 150 > > > > > - connection is not connected to an external port! > > > > > MPD subproperties IOB_STATE=3DBUF|REG or THREE_STATE=3DTRUE req=uire> > > > > that the port > > > > > be connected directly to an external port. > > > > > > Is there any way to work around this? I realize I could just > > > > > connect > > > > > the LCD to the GPIO directly and write software drivers, but I'm > > > > > trying to avoid that because I already have the hardware module i=n> > > > > place and working smoothly. It will also be nice to have this > > > > > separate module so that it does the work of printing to the LCD, =and> > > > > the processor itself can stay busy with other more important jobs=.> > > > > > Also, is there an easier way to add another hardware module witho=ut> > > > > manually editing the generated VHDL files for the core? I'm not > > > > > sure > > > > > if you can do that within Platform Studio. > > > > > > Any advice would be much appreciated, thanks! > > > > > > Ray > > > > That is how the module works so I'll have to try some of these > > > options! The busy signal is set high the entire time data is being > > > written to the LCD. Originally I had a module "program.vhd" that > > > controlled the LCD module along with a keyboard module that we we had > > > in place for user input. Within program.vhd, I implement a state > > > machine and check if the busy signal is high before writing to the > > > LCD. If busy =3D 0, then I set din_ready high and set the 8-bits of > > > data. This is buffered within the LCD module and you only need to > > > hold din_ready for a single cycle to write to the LCD. The LCD is > > > connected over a 4-bit interface to the FPGA and this is taken care o=f> > > within the LCD module. When the writing operation begins busy is set > > > to '1' until complete. > > > > Ray > > > OK - I'm new to using the EDK and am having trouble implementing this > > with the FSL bus. I have a few questions: > > > 1) When I create a custom peripheral, it generates an HDL wrapper - Do > > I simply edit this wrapper by instantiating my LCD_top module as a > > component within the top level design? > > > 2) Should I check the box "Generate template driver files to help you > > implement software interface", or will the provided functions to read > > and write to the FSL bus suffice? > > > 3) Do you know of any good tutorials on how to implement a custom > > peripheral on the FSL bus? I've come across a few for adding > > peripherals to the other buses, but most that I have found do not > > follow through with how to edit the VHDL files and correctly add the > > peripheral to the system in Platform Studio (they simply tell you go > > to 'Create/Import Custom Peripheral'). > > > Any help/input is appreciated, thanks! > > > Ray > > Two more things - > > 1) the four output ports of the LCD module must be connected to the > external FPGA pins in order to drive the LCD. What is the best way to > go about doing this? Is this something that can be edited within > Platform Studio or do I need to manually edit VHDL/UCF files? I'm > assuming I will have to add the outputs to the interface shown below. > > 2) When I choose the master interface for the FSL bus, the ports are > defined as follows: > > -- DO NOT EDIT BELOW THIS LINE --------------------- > -- Bus protocol ports, do not add or delete. > FSL_Clk : in std_logic; > FSL_Rst : in std_logic; > FSL_S_Clk : out std_logic; > FSL_S_Read : out std_logic; > FSL_S_Data : in std_logic_vector(0 to 31); > FSL_S_Control : in std_logic; > FSL_S_Exists : in std_logic; > FSL_M_Clk : out std_logic; > FSL_M_Write : out std_logic; > FSL_M_Data : out std_logic_vector(0 to 31); > FSL_M_Control : out std_logic; > FSL_M_Full : in std_logic > -- DO NOT EDIT ABOVE THIS LINE --------------------- > > You mention that my din(7 downto 0) port should be connected to the > FSL_M_Data port, but the former is an input while the latter is an > output. Am I missing something? I tried to define this as a slave > interface, but that also yields an error when I try to generate the > bitstream. > > Thanks.I think I understand what you are saying, but I'm still unsure of how to implement it. I went through the 'Create and Import Peripheral' wizard to create the pcore and HDL wrapper file, but when you go through this it asks which bus you wish to attach the peripheral to - this generated HDL file is an interface file for the FSL bus, correct? I assumed I needed to edit this file and place my LCD module within this interface file (with the interface shown in my previous message). Do I need to go through this wizard to directly connect to the FSL interface or is this the incorrect method? When you say directly take the MicroBlaze signal and connect them to my module, do you mean edit the aforementioned wrapper file for the pcore, or is there an alternative way? Is there a top level VHD file that I need to edit in order to port the LCD module output to the external FPGA pins? I realize these probably are simple questions but since I've never been through this process within the EDK (and can't find any good tutorials - most deal with adding peripheral to OPB or PLB bus), I'm having a hard time figuring out which steps I need to take in order to accomplish what you have suggested. Anyway, I really do appreciate all your help so far. Thank you! Ray
