Change clock domain for FIFO ...

Hi,

I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner 
in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and 
serializes them to ASI. The serialization works well simulating a Null 
Packet as input.

Now I have to take data from the tuner with unknown clock. I had thought of 
a async FIFO. The clock of the tuner to the left of fifo, to the right my 
clock. Checking the level of fifo and inserting Null packet if necessary.

But how can clocking the fifo directly by the tuner without problems ?

Do you have an example of VHDL code that I could use ?

Thanks.

Kappa.

Kappa wrote:
> Hi,
> 
> I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner 
> in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and 
> serializes them to ASI. The serialization works well simulating a Null 
> Packet as input.
> 
> Now I have to take data from the tuner with unknown clock. I had thought of 
> a async FIFO. The clock of the tuner to the left of fifo, to the right my 
> clock. Checking the level of fifo and inserting Null packet if necessary.
> 

That sounds quite reasonable as this is a typical usage of a fifo 
(switching between clock domains).

> But how can clocking the fifo directly by the tuner without problems ?
> 
 > Do you have an example of VHDL code that I could use ?

Well depending on the device you use there might be some small hacks to 
think of (e.g. Virtex-4 BRAMs in FIFO mode need at least 3 cycles of the 
slowest clock to do a reset). Nevertheless both of the two major FPGA 
vendors offer quite stable implementations for FIFOs. So what exactly 
are You looking for?

Anyway what do You mean with "unknown clock"? Does the frequency vary 
while in use or is the clock stable for a type of tuner and another 
tuner has a different frequency? What about the jitter of the clock?

Regards,

Lorenz

"Kappa" <78kappa78(at)virgilio(dot)it> wrote:

>Hi,
>
>I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner 
>in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and 
>serializes them to ASI. The serialization works well simulating a Null 
>Packet as input.
>
>Now I have to take data from the tuner with unknown clock. I had thought of 
>a async FIFO. The clock of the tuner to the left of fifo, to the right my 
>clock. Checking the level of fifo and inserting Null packet if necessary.
>
>But how can clocking the fifo directly by the tuner without problems ?

This is sort of a text book example. The easiest way though is to
clock the FIFO at the highest frequency and create clock domain
transfer logic at the interface with the lowest frequency. This way
you keep your FIFO at one clock frequency and put the tricky part in a
relative simple piece of logic.


-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Thanks Lorenz,

> Well depending on the device you use there might be some small hacks to
> think of (e.g. Virtex-4 BRAMs in FIFO mode need at least 3 cycles of the
> slowest clock to do a reset). Nevertheless both of the two major FPGA
> vendors offer quite stable implementations for FIFOs. So what exactly
> are You looking for?

I use a Virtex-4 SX35 and Spartan-3E 500 ...

> Anyway what do You mean with "unknown clock"? Does the frequency vary
> while in use or is the clock stable for a type of tuner and another
> tuner has a different frequency? What about the jitter of the clock?

Exactly. The clock input can vary from a minimum of 125 Hz to a
maximum of 11250000 Hz. Some problem could be the first to power up.

Any idea ?

Regards,

Kappa

Hi,

> This is sort of a text book example. The easiest way though is to
> clock the FIFO at the highest frequency and create clock domain
> transfer logic at the interface with the lowest frequency. This way
> you keep your FIFO at one clock frequency and put the tricky part in a
> relative simple piece of logic.

I am okay. Sample with my clock against the rising clock of tuner and
this enabled the writing of FIFO ?

Some code ?

Regards,

Kappa.

<secureasm@gmail.com> wrote in message 
news:2a44c6bc-5647-4ba4-95b3-f3b9cd176a2d@34g2000hsh.googlegroups.com...
> Hi,
>
>
> I am okay. Sample with my clock against the rising clock of tuner and
> this enabled the writing of FIFO ?
>
> Some code ?
>

1. Search the web site of whatever vendor you plan to implement this in for 
a dual clock fifo.
2. Instantiate that component

Alternatively, google for
- lpm_fifo_dc (dual clock fifo) and you should be able to run across the 
source code.  Altera's code is in a file called 220model.vhd which you get 
with Quartus.
- Opencores.org probably has something
- 'dual clock fifo' will probably have some hits as well.

It's not hard, do some research.

KJ 

Thanks KJ,

> 1. Search the web site of whatever vendor you plan to implement this in for
> a dual clock fifo.
> 2. Instantiate that component
>
> Alternatively, google for
> - lpm_fifo_dc (dual clock fifo) and you should be able to run across the
> source code.  Altera's code is in a file called 220model.vhd which you get
> with Quartus.
> - Opencores.org probably has something
> - 'dual clock fifo' will probably have some hits as well.

I do not search 'dual clock fifo', thanks. But i search a interface
code for place a external clock + data to 'dual clock fifo' for first
domain clock. The dual clock fifo is ready. I still want to link the
'Tuner'.

Regards,

Kappa.

A dual-clock (also called asynchronous FIFO) is complex inside because
of the flag control, but is very easy to use:
The input port and the output port are completely separate. You put in
data at any rate, and you pull it out at any other rare you desire.
There is a Full flag that tells you tonstop writing into it, and there
is an Empty flag that tells you to stop reding from it. End of story.
It acts like the waiting room at the doctor's office...
Peter Alfke

On Jul 20, 10:06 am, "Kappa" <78kappa78(at)virgilio(dot)it> wrote:
> Hi,
>
> I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner
> in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and
> serializes them to ASI. The serialization works well simulating a Null
> Packet as input.
>
> Now I have to take data from the tuner with unknown clock. I had thought of
> a async FIFO. The clock of the tuner to the left of fifo, to the right my
> clock. Checking the level of fifo and inserting Null packet if necessary.
>
> But how can clocking the fifo directly by the tuner without problems ?
>
> Do you have an example of VHDL code that I could use ?
>
> Thanks.
>
> Kappa.

I'm not sure what your application is, but for DVB-ASI you might also
want to make sure that you do any PCR restamping, if needed, on the
appropriate side of the FIFO. If you blindly dump your data into some
clock-crossing FIFO you'll wind up introducing extra PCR accuracy
jitter.

 - Kenn

secureasm@gmail.com wrote:

> 
> Exactly. The clock input can vary from a minimum of 125 Hz to a
> maximum of 11250000 Hz. Some problem could be the first to power up.
> 
> Any idea ?
> 

Well, I'd give it a try and directly connect that clock on the producer 
(write-) side of the FIFO. Only if that does not work (though I think it 
will) You should consider sampling the data yourself using a clock with 
at least 22500000 Hz, but I'd not recommand that, as sampling might 
really bring You some unexpected results.
Nevertheless if you have to: I'd design some kind of "edge detection" 
for the input clock (saving the last value and comparing it to the 
current value) and sampling then whenever you detect an edge.
You might also want to consider sampling only with falling edge 
depending on when the data is stable compared to the clock's edges

> Regards,
> 
> Kappa
> 

Regards,

Lorenz