audio serial port i2s

Hi

I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
BCK and LRCK and one data line. I thought it would be good to have
ability to change state of PCM codec between master and slave. In
master mode codec generates both LRCK and BCK clock lines, which are
connected tp my FPGA. In slave mode i need to generate that signals.
Now question - having clock master connected to FPGA (GCLKx Pin) with
12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
= 44100 Mhz ?  Another question is  should i use GCLK pins as input/
output for that clocks or it doesn't matter ?

best regards
wj

>Hi
>
>I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
>FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
>BCK and LRCK and one data line. I thought it would be good to have
>ability to change state of PCM codec between master and slave. In
>master mode codec generates both LRCK and BCK clock lines, which are
>connected tp my FPGA. In slave mode i need to generate that signals.
>Now question - having clock master connected to FPGA (GCLKx Pin) with
>12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
>= 44100 Mhz ?  Another question is  should i use GCLK pins as input/
>output for that clocks or it doesn't matter ?
>
>best regards
>wj
>

My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
that you need a different master clock frequency, or you will have
jitter-related problems.

Whatever you do about the above, don't use GCLK pins. When LRCK is an
input, treat it as a data signal, sample it with the system clock, and
detect the edges as per normal good practice.

On Jul 21, 9:11 am, woj...@gmail.com wrote:
> Hi
>
> I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
> FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
> BCK and LRCK and one data line. I thought it would be good to have
> ability to change state of PCM codec between master and slave. In
> master mode codec generates both LRCK and BCK clock lines, which are
> connected tp my FPGA. In slave mode i need to generate that signals.
> Now question - having clock master connected to FPGA (GCLKx Pin) with
> 12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
> = 44100 Mhz ?  Another question is  should i use GCLK pins as input/
> output for that clocks or it doesn't matter ?
>
> best regards
> wj

I can't answer your questions since they depend on the CODEC more than
anything.  But I just did a design with an AKM codec and used it in
slave mode generating the clocks in the FPGA.  It worked perfectly the
first time I tried it!  No debugging necessary.  I also connected all
of the control signals from the CODEC to the FPGA, but hold them in a
constant state.  This allows me to change the sample rate for other
apps.

I am pretty sure the GCLK pin can be used as a general I/O pin, so you
can output the clock as well as input it.  But the 12.288 clock won't
come from your CODEC will it?  Does this CODEC have a crystal osc in
it?  I think the 12.288 MHz clock is always an input to the CODEC.

BTW, the CODEC I am using is the AK4556 in a small 20 pin TSSOP.  Not
hard to solder, is only 6.5 x 6.5 mm, under $3, less than 100 mW and
samples from 8 to 192 kHz.  All analog I/O is single ended.

Rick

On Jul 21, 10:13 am, "RCIngham" <robert.ing...@gmail.com> wrote:

> My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> that you need a different master clock frequency, or you will have
> jitter-related problems.

12.288 MHz is very typical, because dividing by 256 gives 48 Ksps
which is the typical digital audio sample rate when compatibility with
a CD is not required.  256 also has a lot of power of two factors,
making it possible to have a 32fs or whatever bit clock.

Maybe the OP can run the design at 48 Ksps?

> My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> that you need a different master clock frequency, or you will have
> jitter-related problems.


Are You sure with that ? Most clock diveders work as a counters and
when counter overflowes, output changes state. So if I use 12.288 as
main clock and count from 1 to 256 i get output changed with 44100 Hz.
Or maybe i made mistake somewhere...

On 21 Lip, 17:06, woj...@gmail.com wrote:
> > My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> > that you need a different master clock frequency, or you will have
> > jitter-related problems.
>
> Are You sure with that ? Most clock diveders work as a counters and
> when counter overflowes, output changes state. So if I use 12.288 as
> main clock and count from 1 to 256 i get output changed with 44100 Hz.
> Or maybe i made mistake somewhere...

My mistake, i mean of course 48 kHz

<wojjed@gmail.com> schrieb im Newsbeitrag 
news:56f313a4-cf72-4d40-b478-876b1d7f709e@w7g2000hsa.googlegroups.com...
> Hi
>
> I was thinking about interfacing PCM4204 audio codec by TI with Xilinx
> FPGA XC3S200. Audio serial port I2S needs 3 lines - two clock lines
> BCK and LRCK and one data line. I thought it would be good to have
> ability to change state of PCM codec between master and slave. In
> master mode codec generates both LRCK and BCK clock lines, which are
> connected tp my FPGA. In slave mode i need to generate that signals.
> Now question - having clock master connected to FPGA (GCLKx Pin) with
> 12.288 Mhz frequency - can i divide that clock by 256 to have my LRCK
> = 44100 Mhz ?  Another question is  should i use GCLK pins as input/
> output for that clocks or it doesn't matter ?
>
> best regards
> wj

Yes you can divide your 12.288MHz clock for LRCLK (WS) and BITCLK (SCK).
A simple sync up counter generates an adequate I2S phase relationship.
see:
http://www.nxp.com/acrobat_download/various/I2SBUS.pdf

Use GCLK for the 12.288MHz master clock input, all other generated signals 
can be normal I/Os.

Check if thee is a timing contraint between the ADC system clock (here 
12.288MHz) and the lower ADC clocks.

A master clock of 2x or 4x 12.288MHz (49.152MHz) allows equal clock to 
output times for all ADC signals.

MIKE

-- 
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !
Kontakt:
Tel: 08131 339230
mr@oho-elektronik.de
Usst.ID: DE130097310 

On Jul 21, 11:06 am, woj...@gmail.com wrote:
> > My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> > that you need a different master clock frequency, or you will have
> > jitter-related problems.
>
> Are You sure with that ? Most clock diveders work as a counters and
> when counter overflowes, output changes state. So if I use 12.288 as
> main clock and count from 1 to 256 i get output changed with 44100 Hz.
> Or maybe i made mistake somewhere...

Yes, you made a mistake.  Dividing 12288 kHz by 256 you get 48 kHz.

I don't remember for sure what the basis of 44100 Hz was, but I think
it has to do with being compatible with TV scan rates.  It is
divisible by both 50 Hz and 60 Hz.  But then so is 48,000 Hz.  44100
has as divisors, a pair each of 2, 3, 5 and 7.  I'm not sure why this
is, but the sevens make it incompatible with most standard clock rates
for audio.  The lowest clock rate I can find that is a multiple of
both 48 kHz and 44.1 kHz and above 10 MHz (to run sigma-delta
converters) is 14.112 MHz.  But this gives you some real oddball
divisor values that I don't think CODECs commonly support when using
48 kHz sample rate.

Rick

On 21 Lip, 19:17, woj...@gmail.com wrote:
> On 21 Lip, 17:06, woj...@gmail.com wrote:
>
> > > My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> > > that you need a different master clock frequency, or you will have
> > > jitter-related problems.
>
> > Are You sure with that ? Most clock diveders work as a counters and
> > when counter overflowes, output changes state. So if I use 12.288 as
> > main clock and count from 1 to 256 i get output changed with 44100 Hz.
> > Or maybe i made mistake somewhere...
>
> My mistake, i mean of course 48 kHz

Another question - if i have 4 codecs, where each is connected to
differnet bank (bank0-4) - should each bank have to have its own
clock ? or may i have one master clock connected to GCLK0 ? I have
studied datasheet from xilinx but i have not found answer for that
question.

On Jul 21, 1:47 pm, woj...@gmail.com wrote:
> On 21 Lip, 19:17, woj...@gmail.com wrote:
>
> > On 21 Lip, 17:06, woj...@gmail.com wrote:
>
> > > > My calculator says that 12.288 MHz / 44100 Hz = 278.63946, which suggests
> > > > that you need a different master clock frequency, or you will have
> > > > jitter-related problems.
>
> > > Are You sure with that ? Most clock diveders work as a counters and
> > > when counter overflowes, output changes state. So if I use 12.288 as
> > > main clock and count from 1 to 256 i get output changed with 44100 Hz.
> > > Or maybe i made mistake somewhere...
>
> > My mistake, i mean of course 48 kHz
>
> Another question - if i have 4 codecs, where each is connected to
> differnet bank (bank0-4) - should each bank have to have its own
> clock ? or may i have one master clock connected to GCLK0 ? I have
> studied datasheet from xilinx but i have not found answer for that
> question.

The clocks are independent of the banks, so one clock can drive the
entire chip.

Rick