Hello friends, i have written uart module in vhdl,i have verified using xilinx simulator,but now when i have generated the core of icon,ila and vio,i am unable to get correct output in vio console. i have inputs as clk rst write read din(7 downto 0) output as dout(7 downto 0) i have given in xilinx simulator like this clk connected to C9 on kit rst-------------------------------------- ------------------------------------------ write--------------------------------------------------- ---------------------------------------- ---------------------------------------- read ------------------------------------------------- din 10101010 dout 10101010 when i give 10101010 as input i should get 10101010 as output but i get 11111111 as output u can see the above wave form when write is high then read is low and when read is high write is low,how can i specify in vio console. i am using toggle button to write and read signals.i am not using any clock divider,is it required? what ever i do i just get 11111111. Thanks in advace Irfan
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Started by ●July 25, 2008