Creating new operators

In VHDL an operator can be overloaded.  But can a new operator be
created?  There is more than once I would like to use the very concise
notation available in Verilog such as the select operator.  Is there a
way to create the selection operator in VHDL?  Looking at the
structure, I guess it just doesn't fit the mold for VHDL with three
operands.

I know I can create a function for this such as select(sel,a,b), but I
like the form of the notation sel ? a : b, very clear and concise.  I
guess I could always switch to Verilog... :^)

Rick

On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:

>In VHDL an operator can be overloaded.  But can a new operator be
>created?  There is more than once I would like to use the very concise
>notation available in Verilog such as the select operator.  Is there a
>way to create the selection operator in VHDL?  Looking at the
>structure, I guess it just doesn't fit the mold for VHDL with three
>operands.

No, you can't create new VHDL operators.  Apart from 
introducing new pseudo-keywords into the language, this would
also raise the nasty difficulty that operators have many other
hidden properties apart from their function signature. 
Operators have precedence and associativity.  And of course,
as you say, VHDL has no notion of 3-ary operators like ?:
in any case.

Algol-68 tried to make it possible to create arbitrary 
user-defined operators, and it was VERY complicated...

>I know I can create a function for this such as select(sel,a,b), but I
>like the form of the notation sel ? a : b, very clear and concise.  I
>guess I could always switch to Verilog... :^)

If that's sufficient reason for you to ditch VHDL in favour
of Verilog, I put it to you that your priorities are in need
of some readjustment :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
>
>>In VHDL an operator can be overloaded.  But can a new operator be
>>created?  There is more than once I would like to use the very concise
>>notation available in Verilog such as the select operator.  Is there a
>>way to create the selection operator in VHDL?  Looking at the
>>structure, I guess it just doesn't fit the mold for VHDL with three
>>operands.
>
>No, you can't create new VHDL operators.  Apart from 
>introducing new pseudo-keywords into the language, this would
>also raise the nasty difficulty that operators have many other
>hidden properties apart from their function signature. 
>Operators have precedence and associativity.  And of course,
>as you say, VHDL has no notion of 3-ary operators like ?:
>in any case.
>
>Algol-68 tried to make it possible to create arbitrary 
>user-defined operators, and it was VERY complicated...

More dynamic OO languages support arbitrary operator creation; Smalltalk
would be an example, or the old Linn Lingo.

It's not VERY complicated _in_that_environment_ where static typing is
almost non-existent (strong typing can be rigorous, but implemented at
runtime) BUT ...
(1) you are limited to the creation of binary operators; so ?: is still
tricky, to put it mildly, and
(2) operator precedence is usually predetermined and deeply embedded in
the parser. The above languages solved this problem by allocating
precisely one precedence level to all operators - in other words, use
brackets.

I suspect extensible operator precedence was the main complexity in
ALGOL-68. 

But anyway I suspect you'd have to destroy VHDL to add extensible
operators...

>>I know I can create a function for this such as select(sel,a,b), but I
>>like the form of the notation sel ? a : b, very clear and concise.  I
>>guess I could always switch to Verilog... :^)

It may be personal preference, but I find if-then-else MUCH easier to
read in somebody else's code.

?: does save a few of those precious characters though.

- Brian

On Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
>
>
>
> <jonathan.brom...@MYCOMPANY.com> wrote:
> >On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
>
> >>In VHDL an operator can be overloaded.  But can a new operator be
> >>created?  There is more than once I would like to use the very concise
> >>notation available in Verilog such as the select operator.  Is there a
> >>way to create the selection operator in VHDL?  Looking at the
> >>structure, I guess it just doesn't fit the mold for VHDL with three
> >>operands.
>
> >No, you can't create new VHDL operators.  Apart from
> >introducing new pseudo-keywords into the language, this would
> >also raise the nasty difficulty that operators have many other
> >hidden properties apart from their function signature.
> >Operators have precedence and associativity.  And of course,
> >as you say, VHDL has no notion of 3-ary operators like ?:
> >in any case.
>
> >Algol-68 tried to make it possible to create arbitrary
> >user-defined operators, and it was VERY complicated...
>
> More dynamic OO languages support arbitrary operator creation; Smalltalk
> would be an example, or the old Linn Lingo.
>
> It's not VERY complicated _in_that_environment_ where static typing is
> almost non-existent (strong typing can be rigorous, but implemented at
> runtime) BUT ...
> (1) you are limited to the creation of binary operators; so ?: is still
> tricky, to put it mildly, and
> (2) operator precedence is usually predetermined and deeply embedded in
> the parser. The above languages solved this problem by allocating
> precisely one precedence level to all operators - in other words, use
> brackets.
>
> I suspect extensible operator precedence was the main complexity in
> ALGOL-68.
>
> But anyway I suspect you'd have to destroy VHDL to add extensible
> operators...
>
> >>I know I can create a function for this such as select(sel,a,b), but I
> >>like the form of the notation sel ? a : b, very clear and concise.  I
> >>guess I could always switch to Verilog... :^)
>
> It may be personal preference, but I find if-then-else MUCH easier to
> read in somebody else's code.
>
> ?: does save a few of those precious characters though.
>
> - Brian

The problem is not so much reading the code, but is writing.  I think
in the terms of the logic, usually a schematic/block diagram.  Then I
try to express that logic in the language.  It is not uncommon that it
is simply impossible to express the logic in the form I have drawn
it.  Then I have to convolute it to come up with something that is
what I have drawn, or at least I hope so.

Example: A data mux controlled by the output of an AND of a signal and
the output of a mux.  This is four control signals gated together to
drive the control on the data mux.  Here is what I ended up with.

  BERTEn <=	'0' when BERTSel = '0' else
		not SyncPOSSel when GenEn = '0' else
		not GenPOSSel;

I don't think that the diagram I drew comes to mind when you see this
code.  Maybe a process with an IF statement would be slightly more
clear, but the verbosity presents an obfuscation of its own from the
"clutter" created.

process (  BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
  if (BERTSel = '0') then
    BERTEn <=	'0';
  elsif (GenEn = '0') then
    BERTEn <=	not SyncPOSSel
  else
    BERTEn <=	not GenPOSSel;
  end if;
end process;

The clutter is from the sheer size of the code.  The first three line
example is a bit obtuse, the 9 line example is large enough to make it
hard to see the rest of the code and so to see how it fits into the
big picture.  Compare the two examples to this code...

  BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

This is what I expect a concurrent statement to look like, not to
mention that it represents exactly the image I had in my head and on
the whiteboard, making it much easier to write.

I am sure there are those who disagree and much prefer the verbose
process.  Maybe I'm just not cut out for the regimen of VHDL.

Rick

rickman wrote:

>   BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

     if BERTSel and GenEn then
        BERTEn <= not SyncPOSSel;
     else
        BERTEn <= not GenPOSSel;
     end if;

"rickman" <gnuarm@gmail.com> wrote in message 
news:62e47371-9d8d-43d1-a97b-4759ecc35fc6@56g2000hsm.googlegroups.com...
.
>
> I know I can create a function for this such as select(sel,a,b), but I
> like the form of the notation sel ? a : b, very clear and concise.

This is nearly as concise and what I use.

x<= sel(Condition, a, b);

You would have to overload 'sel' to handle all the data types that you deal 
with (std_(u)logic(_vector), integer, real, time, etc).  These could be 
written once and then put into a common package that you use with wild 
abandon.  More specialized types that are application specific like records 
would then need similar overrides (if needed).

> I
> guess I could always switch to Verilog... :^)
>

If that's the best reason you got, then you cna have it.

KJ 

rickman wrote:

>   BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

This is not the same logic as you described with your initial example.

> This is what I expect a concurrent statement to look like, not to
> mention that it represents exactly the image I had in my head and on
> the whiteboard, making it much easier to write.

What about this one:

BERTEn <= (not SyncPOSSel) when (BERTSel='1' and GenEn='1')
            else (not GenPOSSel);

The parantheses are not necessary, but helps reading it.

I don't like elsif and I would write your initial example like this:

	process (BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
		if BERTSel = '0' then
			BERTEn <= '0';
		else
			if GenEn = '0' then
				BERTEn <= not SyncPOSSel;
			else
				BERTEn <= not GenPOSSel;
			end if;
		end if;
	end process;

Some more code, but you don't have to think about when reading it, because
it shows the hierarchically structure, which is only implicit in your code.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

On Jul 26, 9:38 am, Mike Treseler <mtrese...@gmail.com> wrote:
> rickman wrote:
> >   BERTEn <=     BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
>      if BERTSel and GenEn then
>         BERTEn <= not SyncPOSSel;
>      else
>         BERTEn <= not GenPOSSel;
>      end if;

One of us doesn't understand the precedence (I'm not sure which
one...).  That is always a good reason for not allowing precedence
defaults to define an expression...

   BERTEn <=     BERTSel and (GenEn ? not SyncPOSSel : not GenPOSSel);

Is that more clear?

Rick

On Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
> rickman wrote:
> >   BERTEn <=     BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
> This is not the same logic as you described with your initial example.
>
> > This is what I expect a concurrent statement to look like, not to
> > mention that it represents exactly the image I had in my head and on
> > the whiteboard, making it much easier to write.
>
> What about this one:
>
> BERTEn <= (not SyncPOSSel) when (BERTSel='1' and GenEn='1')
>             else (not GenPOSSel);
>
> The parantheses are not necessary, but helps reading it.
>
> I don't like elsif and I would write your initial example like this:
>
>         process (BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
>                 if BERTSel = '0' then
>                         BERTEn <= '0';
>                 else
>                         if GenEn = '0' then
>                                 BERTEn <= not SyncPOSSel;
>                         else
>                                 BERTEn <= not GenPOSSel;
>                         end if;
>                 end if;
>         end process;
>
> Some more code, but you don't have to think about when reading it, because
> it shows the hierarchically structure, which is only implicit in your code.

You got the same result as Mike, so I assume I had the precedence
default wrong.  No, I guess there is *no* precedence since there is no
selection operator.  This is what I intended.  To make it more VHDL
like, I need to add an equivalence operator too.

   BERTEn <=     BERTSel and ((GenEn = '1') ? not GenPOSSel : not
SyncPOSSel);

The process based description is not immediately clear to me at first
glance.  I *do* have to think about it since that is not what I
picture in my mind.  I visualize a MUX controlled by GenEn feeding an
AND gate with BERTSel.  The Verilog like assignment maps exactly to
that visualization.  The others require me to mentally convert the
syntax from and IF statement to the AND gate not to mention the length
of the code.  But like I said, it is not that this is hard to
understand, it is not what I pictured in my mind and so I had to
perform a conversion from the logic to the syntax.  That takes time
and is a distraction from making my work accurate.

I have no doubt that others may find that verbose code is easier for
them to read.  But I find concise code is best (but not too!
concise).  There are any number of different logic forms to be
expressed and each is expressed best in different ways.  I think the
selection statement is an operator that has a useful place in VHDL.
I'm just sorry it wasn't included.  I guess it would have been hard to
provide for overloading since it does not fit the standard uniary or
binary format.

Rick

"rickman" <gnuarm@gmail.com> wrote in message 
news:f3419e72-2cf2-4a01-8300-c5184afc38f7@34g2000hsh.googlegroups.com...
> On Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
>> rickman wrote:

>
> The process based description is not immediately clear to me at first
> glance.  I *do* have to think about it since that is not what I
> picture in my mind.  I visualize a MUX controlled by GenEn feeding an
> AND gate with BERTSel.  The Verilog like assignment maps exactly to
> that visualization.  The others require me to mentally convert the
> syntax from and IF statement to the AND gate not to mention the length
> of the code.  But like I said, it is not that this is hard to
> understand, it is not what I pictured in my mind and so I had to
> perform a conversion from the logic to the syntax.  That takes time
> and is a distraction from making my work accurate.
>
> I have no doubt that others may find that verbose code is easier for
> them to read.  But I find concise code is best (but not too!
> concise).  There are any number of different logic forms to be
> expressed and each is expressed best in different ways.  I think the
> selection statement is an operator that has a useful place in VHDL.
> I'm just sorry it wasn't included.  I guess it would have been hard to
> provide for overloading since it does not fit the standard uniary or
> binary format.
>
> Rick

So why do you not use schematic capture tools for your designs - or is that 
too uncool?

Icky