Cyclone III passive serial config issue

Hi, my name is Paul, and I'm a long-time Xilinx user.  (in your best AA 
voice, now: "Hi Paul") I'm doing my first Altera design using a Cyclone 
III. The design has a very wide video output bus which drives some 
ASICs, so the VCCIO voltage is set to 3.0 so the internal series 
terminations can be used.

I believe I understand the interface rules when VCCIO = 3.0V, but now 
the relationship between the configuration modes and VCCIO for a given 
configuration banks is a bit unclear.

I plan to use one of the Passive Serial configuration modes and Table 
10-1 in the Cyclone III Handbook shows the following.

     Config. Scheme       | MSEL[3:0] | Config. Voltage Std
-------------------------+-----------+--------------------
Passive Serial Standard  |    0000   |  3.3/2.5 V
Active Serial Standard   |    0010   |  3.3 V
Active Parallel �16 Fast |    0101   |  3.3 V
Active Parallel �16 Fast |    0110   |  1.8 V
Active Parallel �16      |    0111   |  3.3 V
Active Parallel �16      |    1000   |  1.8 V
Active Parallel �16      |    1011   |  3.0/2.5 V
Passive Serial Fast      |    1100   |  3.3/2.5 V
Active Serial Fast       |    1101   |  3.3 V
Fast Passive Par. Fast   |    1110   |  3.3/2.5 V
Fast Passive Par. Fast   |    1111   |  1.8/1.5 V
JTAG-based configuration |    XXXX   |   �

X = Valid low or high level


 From the above table, it appears that the MSEL pins have different 
values for the same configuration mode, with the only difference being 
the VCCIO level.

What is unclear (or rather, a potential problem) is that for both 
passive serial modes, the configuration voltage standard is 3.3/2.5V. 
Note that 3.0V is conspicuously absent for the passive serial modes. In 
fact, the only configuration mode which lists 3.0V is Active Parallel.

Does this mean that I can't use any configuration mode except Active 
Parallel (and JTAG) if all of my VCCIO levels are at 3.0V?


TIA

Paul

If you are using passive serial, like the table ground msel[..0] and
you are done.
3.3/2.5V just means CIII parts are OK with those voltage, but use
3.0V(MAX) for all you IO and pull ups where needed

On Jul 27, 9:25=A0am, Paul Urbanus <urbpub...@hotmail.com> wrote:
> Hi, my name is Paul, and I'm a long-time Xilinx user. =A0(in your best AA
> voice, now: "Hi Paul") I'm doing my first Altera design using a Cyclone
> III. The design has a very wide video output bus which drives some
> ASICs, so the VCCIO voltage is set to 3.0 so the internal series
> terminations can be used.
>
> I believe I understand the interface rules when VCCIO =3D 3.0V, but now
> the relationship between the configuration modes and VCCIO for a given
> configuration banks is a bit unclear.
>
> I plan to use one of the Passive Serial configuration modes and Table
> 10-1 in the Cyclone III Handbook shows the following.
>
> =A0 =A0 =A0Config. Scheme =A0 =A0 =A0 | MSEL[3:0] | Config. Voltage Std
> -------------------------+-----------+--------------------
> Passive Serial Standard =A0| =A0 =A00000 =A0 | =A03.3/2.5 V
> Active Serial Standard =A0 | =A0 =A00010 =A0 | =A03.3 V
> Active Parallel =D716 Fast | =A0 =A00101 =A0 | =A03.3 V
> Active Parallel =D716 Fast | =A0 =A00110 =A0 | =A01.8 V
> Active Parallel =D716 =A0 =A0 =A0| =A0 =A00111 =A0 | =A03.3 V
> Active Parallel =D716 =A0 =A0 =A0| =A0 =A01000 =A0 | =A01.8 V
> Active Parallel =D716 =A0 =A0 =A0| =A0 =A01011 =A0 | =A03.0/2.5 V
> Passive Serial Fast =A0 =A0 =A0| =A0 =A01100 =A0 | =A03.3/2.5 V
> Active Serial Fast =A0 =A0 =A0 | =A0 =A01101 =A0 | =A03.3 V
> Fast Passive Par. Fast =A0 | =A0 =A01110 =A0 | =A03.3/2.5 V
> Fast Passive Par. Fast =A0 | =A0 =A01111 =A0 | =A01.8/1.5 V
> JTAG-based configuration | =A0 =A0XXXX =A0 | =A0 =97
>
> X =3D Valid low or high level
>
> =A0From the above table, it appears that the MSEL pins have different
> values for the same configuration mode, with the only difference being
> the VCCIO level.
>
> What is unclear (or rather, a potential problem) is that for both
> passive serial modes, the configuration voltage standard is 3.3/2.5V.
> Note that 3.0V is conspicuously absent for the passive serial modes. In
> fact, the only configuration mode which lists 3.0V is Active Parallel.
>
> Does this mean that I can't use any configuration mode except Active
> Parallel (and JTAG) if all of my VCCIO levels are at 3.0V?
>
> TIA
>
> Paul