RTL Schematic as EDIF

Hi!

My PhD thesis deals with coarse-grained reconfigurable logic. Therefore
the RTL schematic synthesis result is one major input for my work.

I tried Xilinx ISE 10.1 as well as Synplicity Synplify Pro 9.2. Both
tools provide this RTL netlist (before implementing it to the technology
netlist), but both in encrypted file formats.

Xilinx ISE 10.1 saves the file as NGR file. Unfortunately there is no
ngr2edif tool provided (while an ngc2edif is available). 

Synplicity Synplify Pro 9.2 saves a SRS file and provides an edf2srs
tool, but no reverse.

Could you please point me to tools which can convert these files formats
to open formats (especially EDIF) or to synthesis tools (not necessarily
for FPGA, a tool from an ASIC flow is ok too), which save the RTL
schematic as open file formats.

Thanks
  Hansi

-- 
Johann Glaser                          <glaser@ict.tuwien.ac.at>
             Institute of Computer Technology, E384
Vienna University of Technology, Gusshausstr. 27-29, A-1040 Wien
Phone: ++43/1/58801-38444                Fax: ++43/1/58801-38499

On Thu, 07 Aug 2008 11:29:43 +0200, Johann Glaser wrote:

>Hi!
>
>My PhD thesis deals with coarse-grained reconfigurable logic. Therefore
>the RTL schematic synthesis result is one major input for my work.
>
>I tried Xilinx ISE 10.1 as well as Synplicity Synplify Pro 9.2. Both
>tools provide this RTL netlist (before implementing it to the technology
>netlist), but both in encrypted file formats.

Yes, but every synth tool can write out a post-synthesis netlist
in VHDL or Verilog ready for functional simulation.  Sure you 
don't get a schematic, but I would have thought that a VHDL
or Verilog netlist of primitives would be just as good.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Hi!

Am Donnerstag, den 07.08.2008, 13:31 +0100 schrieb Jonathan Bromley:
> On Thu, 07 Aug 2008 11:29:43 +0200, Johann Glaser wrote:
> 
> >Hi!
> >
> >My PhD thesis deals with coarse-grained reconfigurable logic. Therefore
> >the RTL schematic synthesis result is one major input for my work.
> >
> >I tried Xilinx ISE 10.1 as well as Synplicity Synplify Pro 9.2. Both
> >tools provide this RTL netlist (before implementing it to the technology
> >netlist), but both in encrypted file formats.
> 
> Yes, but every synth tool can write out a post-synthesis netlist
> in VHDL or Verilog ready for functional simulation.  Sure you 
> don't get a schematic, but I would have thought that a VHDL
> or Verilog netlist of primitives would be just as good.

The schematic itself is not important for me, the netlist is the thing I
want. For my research project I need the RTL netlist because it holds
"higher level" information, like e.g. counters, MUXes, ... A technology
mapped netlist is of no use for me, because the "interesting" things
have already gone there.

The HDL netlist is quite nice for me, but unfortunately a bit hard to
work with. I'd have to implement a complex parser and as well as some
"small synthesis" algorithms.

Do you know if there is a reason, why synthesis tools refuse the user to
get the RTL netlist as EDIF?

Thanks
  Hansi

Hi,

You might want to take a look at
http://www.eecs.berkeley.edu/~alanmi/abc/
you can download the source, for research
purposes this might be what you need.

--Sandeep 

Johann Glaser wrote:

> The schematic itself is not important for me, the netlist is the thing I
> want. For my research project I need the RTL netlist because it holds
> "higher level" information, like e.g. counters, MUXes, ... 

What's wrong with the source code?
That's the highest level I have,
and the easiest object to simulate.

An RTL schematic shows collections of gates and flops.
Some of the gate collections are drawn as MUXes and
others are drawn as boxes:
http://mysite.verizon.net/miketreseler/uart.pdf

I use these interactively to see what my source
code looks like to synthesis, and for documentation.
However, for simulation or making a synthesis image,
the source is the thing.

> Do you know if there is a reason, why synthesis tools refuse the user to
> get the RTL netlist as EDIF?

Because such a netlist is at a lower level
than the source code that created it, and is
not useful for synthesis.

Back before A+X offered RTL views,
I used to roll my own using Leo to map my design
to a simple FPGA architecture like an Actel 1010.
The resulting technology view looked very much
like today's RTL views.
You could make an edif file of something like that.

     -- Mike Treseler

Johann Glaser <glaser@ict.tuwien.ac.at> wrote:

>Hi!
>
>My PhD thesis deals with coarse-grained reconfigurable logic. Therefore
>the RTL schematic synthesis result is one major input for my work.
>
>I tried Xilinx ISE 10.1 as well as Synplicity Synplify Pro 9.2. Both
>tools provide this RTL netlist (before implementing it to the technology
>netlist), but both in encrypted file formats.
>
>Xilinx ISE 10.1 saves the file as NGR file. Unfortunately there is no
>ngr2edif tool provided (while an ngc2edif is available). 
>
>Synplicity Synplify Pro 9.2 saves a SRS file and provides an edf2srs
>tool, but no reverse.
>
>Could you please point me to tools which can convert these files formats
>to open formats (especially EDIF) or to synthesis tools (not necessarily
>for FPGA, a tool from an ASIC flow is ok too), which save the RTL
>schematic as open file formats.

Why not export to VHDL? It can be regarded as some sort of netlist and
probably converted to EDIF as well. 

-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Johann Glaser wrote:

> 
> The schematic itself is not important for me, the netlist is the thing I
> want. For my research project I need the RTL netlist because it holds
> "higher level" information, like e.g. counters, MUXes, ... A technology
> mapped netlist is of no use for me, because the "interesting" things
> have already gone there.
> 
> The HDL netlist is quite nice for me, but unfortunately a bit hard to
> work with. I'd have to implement a complex parser and as well as some
> "small synthesis" algorithms.
> 
> Do you know if there is a reason, why synthesis tools refuse the user to
> get the RTL netlist as EDIF?
> 
> Thanks
>   Hansi

Lieber Hansi,
The intermiate (RTL) netlist is usually proprietary.  I don't think 
companies want to give this away.  It sounds like you would really like 
a tool like Verific, which is an HDL parser that a lot of companies are 
buying as a front end for their own synthesis (and simulation) tools. 
It outputs an RTL-type netlist, with high level primitive blocks.  I 
don't know how expensive this would be for an individual user to buy, 
though.

I can think of good reasons why the RTL netlist isn't in a standard 
format.  Assume that you really liked the Xilinx synthesizer, because it 
was so great at inferring structures from behavioral code.  You could 
then get that tool (cheap, since it is subsidized), and then take the 
RTL netlist and synthesize it with a poorer synthesizer using another 
part as a target.
-Kevin

Hi Mike!

> > The schematic itself is not important for me, the netlist is the thing I
> > want. For my research project I need the RTL netlist because it holds
> > "higher level" information, like e.g. counters, MUXes, ... 
> 
> What's wrong with the source code?
> That's the highest level I have,
> and the easiest object to simulate.

Some background information to make my intent plausible: In my PhD I'm
investigating how to build custom ultra-low-power logic to a SoC, which
is still configurable. On a continuum of configurability between
fine-grained (e.g. FPGA, CPLD) to coarse-grained (e.g. Cypress PSoC) my
plan is to stay in between. Therefore the RTL netlist, i.e. the first
synthesis step, is near my planned granularity.

For my implementation I need a netlist, with gates and flip-flops. VHDL
or Verilog are too user-dependent and flexible. You are right, in some
way they also describe a netlist, but rather implicitly. I want to use a
synthesis tool to convert this to an explicit netlist. As stated before,
the RTL netlist is exactly what I need for further processing. The
technology mapping will then be done by another tool (or by hand, if
necessary) utilizing my custom configurable blocks.

> An RTL schematic shows collections of gates and flops.
> Some of the gate collections are drawn as MUXes and
> others are drawn as boxes:
> http://mysite.verizon.net/miketreseler/uart.pdf

May I ask which tool you used to generate this netlist and to print it
to a PDF file?

> I use these interactively to see what my source
> code looks like to synthesis, and for documentation.
> However, for simulation or making a synthesis image,
> the source is the thing.

Yes, exactly what it is intended for.

> > Do you know if there is a reason, why synthesis tools refuse the user to
> > get the RTL netlist as EDIF?
> 
> Because such a netlist is at a lower level
> than the source code that created it, and is
> not useful for synthesis.

Hmm, it is indeed useful, because it is then technology-mapped. Most
tools also offer to import RTL netlists as EDIF files. But why do they
refuse to export their work?

Bye
  Hansi

Hi Kevin!

> The intermiate (RTL) netlist is usually proprietary.  I don't think 
> companies want to give this away.  It sounds like you would really like 
> a tool like Verific, which is an HDL parser that a lot of companies are 
> buying as a front end for their own synthesis (and simulation) tools. 
> It outputs an RTL-type netlist, with high level primitive blocks.  I 
> don't know how expensive this would be for an individual user to buy, 
> though.

Thanks for the hint. They have a 30 day trial download, I'll have a look
at that!

Bye
  Hansi

Hi Sandeep

> You might want to take a look at
> http://www.eecs.berkeley.edu/~alanmi/abc/
> you can download the source, for research
> purposes this might be what you need.

Thanks for the hint. These tools are definitely interesting, once
because they are open source, and second because they provide
functionality for my backend tasks.

Bye
  Hansi