I have a Spartan 3E XC3S500E. According to the data sheet, it has 20 blocks of ram, totalling up to 368,640 bits. I've used it for my FIFO core, which is 5bits width and 65k depth. However, the amount of data that I managed to store inside, seems to be way lesser than 368,640bits. Even before reach 100,000bits, the FIFO output a write_full signal, telling me that it's full. I've no other cores, except my own code. Are there any other mechanism that uses the blockram even though it is not indicated on the Summary page inside my Xilinx ISE?
Block Rams
Started by ●August 9, 2008
Reply by ●August 9, 20082008-08-09
"Zhane" <me75@hotmail.com> wrote in message news:4b0f65af-207b-41d6-836d-378947084936@b30g2000prf.googlegroups.com...> However, the amount of data that I managed to store inside, seems to > be way lesser than 368,640bits. Even before reach 100,000bits, the > FIFO output a write_full signal, telling me that it's full. >1. How did you validate the actual number of fifo writes that you performed? Presumably your counter is counting more than once for each time that you think you do a write. 2. What causes the fifo to be written to? Is that signal generated synchronously to the same clock that clocks the fifo?> I've no other cores, except my own code. Are there any other mechanism > that uses the blockram even though it is not indicated on the Summary > page inside my Xilinx ISE?1. Start with a simulation, get that working. 2. Validate that the inputs to the simulation of the device match what is happening on the actual device Since your code is implementing the fifo, keep in mind that the fifo signal is *saying* that the fifo is full, it might not in fact be *full*. Memory does not send out a signal indicating that it is full, logic that counts events does. KJ
Reply by ●August 9, 20082008-08-09
On Aug 9, 4:36=A0pm, Zhane <m...@hotmail.com> wrote:> I have a Spartan 3E XC3S500E. According to the data sheet, it has 20 > blocks of ram, totalling up to 368,640 bits. > > I've used it for my FIFO core, which is 5bits width and 65k depth. > > However, the amount of data that I managed to store inside, seems to > be way lesser than 368,640bits. Even before reach 100,000bits, the > FIFO output a write_full signal, telling me that it's full. > > I've no other cores, except my own code. Are there any other mechanism > that uses the blockram even though it is not indicated on the Summary > page inside my Xilinx ISE?Zhane, you are building a narrow and very deep FIFO. Obviously it does not fit into one BlockRAM. How did you partition it? You should use 5 BRAMs in parallel, each 1 bit wide, and 4 such structures in series for the required depth. That would be most efficient, and would also be fairly simple. This is the only reasonable partitioning. Perhaps you made each BRAM 9 bits wide, and concatenated 20 of them, but that would give you only a depth of about 40k location, since you wasted 4 out of 9 memory locations. You did not mention speed and asynchronous vs synchronous operation. Thus I assume you have no problms there. How did you design the FIFO? Did you use a Wizard, or CoreGen? Peter Alfke, Xilinx Applications
Reply by ●August 9, 20082008-08-09
erm I used the CoreGen to do it. I set it up for 2 independent clocks. Ya.. my writing code is using the same clock as the clock that is fed into the FIFO
Reply by ●August 9, 20082008-08-09
On Aug 10, 7:50=A0am, "KJ" <kkjenni...@sbcglobal.net> wrote:> "Zhane" <m...@hotmail.com> wrote in message > > news:4b0f65af-207b-41d6-836d-378947084936@b30g2000prf.googlegroups.com... > > > However, the amount of data that I managed to store inside, seems to > > be way lesser than 368,640bits. Even before reach 100,000bits, the > > FIFO output a write_full signal, telling me that it's full. > > 1. How did you validate the actual number of fifo writes that you perform=ed?> Presumably your counter is counting more than once for each time that you > think you do a write. > 2. What causes the fifo to be written to? =A0Is that signal generated > synchronously to the same clock that clocks the fifo? > > > I've no other cores, except my own code. Are there any other mechanism > > that uses the blockram even though it is not indicated on the Summary > > page inside my Xilinx ISE? > > 1. Start with a simulation, get that working. > 2. Validate that the inputs to the simulation of the device match what is > happening on the actual device > > Since your code is implementing the fifo, keep in mind that the fifo sign=al> is *saying* that the fifo is full, it might not in fact be *full*. =A0Mem=ory> does not send out a signal indicating that it is full, logic that counts > events does. > > KJmy code is working both in simulation and in real application. Just that when I starts to write a little bit more into the fifo, the fifo's output signal says that it is full and refuse to let me write anymore.
Reply by ●August 9, 20082008-08-09
On Aug 9, 6:43=A0pm, Zhane <m...@hotmail.com> wrote:> erm > > I used the CoreGen to do it. > I set it up for 2 independent clocks. > > Ya.. my writing code is using the same clock as the clock that is fed > into the FIFOZhane, you did not answer my question: How is the FIFO partitioned? What is each BRAM doing? 1 bit wide and 16K deep (as it should) or 9 bits wide and 2K deep (which is bad)? Peter Alfke
Reply by ●August 9, 20082008-08-09
On Aug 10, 10:20=A0am, Peter Alfke <pe...@xilinx.com> wrote:> On Aug 9, 6:43=A0pm, Zhane <m...@hotmail.com> wrote: > > > erm > > > I used the CoreGen to do it. > > I set it up for 2 independent clocks. > > > Ya.. my writing code is using the same clock as the clock that is fed > > into the FIFO > > Zhane, > you did not answer my question: > How is the FIFO partitioned? What is each BRAM doing? > 1 bit wide and 16K deep (as it should) or 9 bits wide and 2K deep > (which is bad)? > Peter AlfkeI dont know? Is it specified in the CoreGen?
Reply by ●August 10, 20082008-08-10
On Sat, 9 Aug 2008 19:24:28 -0700 (PDT), Zhane <me75@hotmail.com> wrote:>On Aug 10, 10:20�am, Peter Alfke <pe...@xilinx.com> wrote: >> On Aug 9, 6:43�pm, Zhane <m...@hotmail.com> wrote:>> Zhane, >> you did not answer my question: >> How is the FIFO partitioned? What is each BRAM doing? >> 1 bit wide and 16K deep (as it should) or 9 bits wide and 2K deep >> (which is bad)? >> Peter Alfke > >I dont know? Is it specified in the CoreGen?Coregen writes a simulation model, which is a normal VHDL file. You can read that and see which simulation primitives it has used, e.g. RAMB16_something. These you can look up in the Spartan-3 Library Guide, to answer Peter's questions. That will also answer your own questions. - Brian
Reply by ●August 10, 20082008-08-10
On Aug 10, 8:44=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Sat, 9 Aug 2008 19:24:28 -0700 (PDT), Zhane <m...@hotmail.com> wrote: > >On Aug 10, 10:20=A0am, Peter Alfke <pe...@xilinx.com> wrote: > >> On Aug 9, 6:43=A0pm, Zhane <m...@hotmail.com> wrote: > >> Zhane, > >> you did not answer my question: > >> How is the FIFO partitioned? What is each BRAM doing? > >> 1 bit wide and 16K deep (as it should) or 9 bits wide and 2K deep > >> (which is bad)? > >> Peter Alfke > > >I dont know? Is it specified in the CoreGen? > > Coregen writes a simulation model, which is a normal VHDL file. > You can read that and see which simulation primitives it has used, e.g. > RAMB16_something. These you can look up in the Spartan-3 Library Guide, > to answer Peter's questions. That will also answer your own questions. > > - Brianthe vhdl file is only a wrapper file. I dont see any Ram16? How should I find it? =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY fifo_generator_v4_2_5bit IS port ( din: IN std_logic_VECTOR(4 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(4 downto 0); empty: OUT std_logic; full: OUT std_logic); END fifo_generator_v4_2_5bit; ARCHITECTURE fifo_generator_v4_2_5bit_a OF fifo_generator_v4_2_5bit IS -- synthesis translate_off component wrapped_fifo_generator_v4_2_5bit port ( din: IN std_logic_VECTOR(4 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(4 downto 0); empty: OUT std_logic; full: OUT std_logic); end component; -- Configuration specification for all : wrapped_fifo_generator_v4_2_5bit use entity XilinxCoreLib.fifo_generator_v4_2(behavioral) generic map( c_has_int_clk =3D> 0, c_rd_freq =3D> 1, c_wr_response_latency =3D> 1, c_has_srst =3D> 0, c_has_rd_data_count =3D> 0, c_din_width =3D> 5, c_has_wr_data_count =3D> 0, c_full_flags_rst_val =3D> 1, c_implementation_type =3D> 2, c_family =3D> "spartan3", c_use_embedded_reg =3D> 0, c_has_wr_rst =3D> 0, c_wr_freq =3D> 1, c_use_dout_rst =3D> 1, c_underflow_low =3D> 0, c_has_meminit_file =3D> 0, c_has_overflow =3D> 0, c_preload_latency =3D> 1, c_dout_width =3D> 5, c_rd_depth =3D> 65536, c_default_value =3D> "BlankString", c_mif_file_name =3D> "BlankString", c_has_underflow =3D> 0, c_has_rd_rst =3D> 0, c_has_almost_full =3D> 0, c_has_rst =3D> 1, c_data_count_width =3D> 16, c_has_wr_ack =3D> 0, c_use_ecc =3D> 0, c_wr_ack_low =3D> 0, c_common_clock =3D> 0, c_rd_pntr_width =3D> 16, c_use_fwft_data_count =3D> 0, c_has_almost_empty =3D> 0, c_rd_data_count_width =3D> 16, c_enable_rlocs =3D> 0, c_wr_pntr_width =3D> 16, c_overflow_low =3D> 0, c_prog_empty_type =3D> 0, c_optimization_mode =3D> 0, c_wr_data_count_width =3D> 16, c_preload_regs =3D> 0, c_dout_rst_val =3D> "0", c_has_data_count =3D> 0, c_prog_full_thresh_negate_val =3D> 65532, c_wr_depth =3D> 65536, c_prog_empty_thresh_negate_val =3D> 3, c_prog_empty_thresh_assert_val =3D> 2, c_has_valid =3D> 0, c_init_wr_pntr_val =3D> 0, c_prog_full_thresh_assert_val =3D> 65533, c_use_fifo16_flags =3D> 0, c_has_backup =3D> 0, c_valid_low =3D> 0, c_prim_fifo_type =3D> "8kx4", c_count_type =3D> 0, c_prog_full_type =3D> 0, c_memory_type =3D> 1); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_fifo_generator_v4_2_5bit port map ( din =3D> din, rd_clk =3D> rd_clk, rd_en =3D> rd_en, rst =3D> rst, wr_clk =3D> wr_clk, wr_en =3D> wr_en, dout =3D> dout, empty =3D> empty, full =3D> full); -- synthesis translate_on END fifo_generator_v4_2_5bit_a;
Reply by ●August 11, 20082008-08-11
