How to work with global clocks and buffers in CPLD?

Hi:

I have a Verilog design for a Xilinx XPLA3 CPLD consisting of a toplevel 
module that instantiates several other modules.  I am developing in 
WebPACK 5.2i.

The current design requires a single clock signal.  I am supplying that 
clock through one of the INn/CLKn inputs of the XPLA3 architecture.

Must I do anything special in the Verilog in order to ensure that the 
clock is routed through the chip using the dedicated clock distribution 
lines rather than through general purpose logic signal routing?

For instance, should I use BUF, BUFG, and/or BUFSR ?

Thanks for comments.  Exerpts of my code shown below:


 From myproj.ucf file:

NET "Clk10kHz" LOC = "p89";  <--- p89 is IN1/CLK1
NET "Vsync" LOC = "p79";
NET "InhReq" LOC = "p78";
NET "Inhibit" LOC = "p77";
NET "Grab" LOC = "p76";


 From top level Verilog module:

module Cam_Inh_1(Vsync, InhReq, Inhibit, Grab, Clk10kHz);
   input wire Vsync, InhReq, Clk10kHz;
   output wire Inhibit, Grab;

   wire inhibit_out, grab_out;

// In this instantiation of a sub-module, we just pass the clock along

   Cam_Inh CameraInhibit1( .Vsync(~Vsync), .InhReq(~InhReq), 

                           .Inhibit(inhibit_out),
                           .Grab(grab_out), .Clk10kHz(Clk10kHz) );

   assign Inhibit = ~inhibit_out;
   assign Grab = ~grab_out;

endmodule


The module "Cam_Inh" also passes the clock along to lower modules, where 
it finally gets used in a counter.


-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov