Q: Demo Altera NIOS II SOPC limitations

Hi All,

I have just compiled a NIOS II core into Cyclone I part (I was given
an old MJL demo board) and compiled some trivial C. Everything seems
to work as advertised.

I still haven't figured out the time limited nature of the NIOS II
SOPC builder, could someone enlighten me please. There seems to be a
60 minute limit between creating the FPGA code (Verilog) and compiling
a new FPGA image, or does that limit apply to time between compiling
an image and programming a part ?

Also, what is the difference between the web edition and the fully
paid up version of Quartus II.

All tools above are V7.2.

I am only experimenting at the moment and I need to understand the
limitations of the tool chain before I invest too much more time and
effort in this educational project,.

Many thanks,

Mark

On 2008-08-15, MarkAren <markaren10@yahoo.com> wrote:
>
> I still haven't figured out the time limited nature of the NIOS II
> SOPC builder, could someone enlighten me please.

It's 60 minutes of runtime on the part without the JTAG cable
connected.  If you keep the JTAG connection live then you can run
forever.

> Also, what is the difference between the web edition and the fully
> paid up version of Quartus II.

I think NIOS II is sold separately from the subscription Quartus II.
I think you buy NIOS one time and you have a perpetual license for that
version.

It's neat, and I've used the tethered version, but when I built a
Cyclone II project I just threw down a microcontroller rather than use
NIOS II.  $500 will buy a lot of micros.  I think their pricing
model is a mistake -- it keeps hobbiests from doing anything serious
with NIOS II and that keeps those same people from being able to
recommend it for "serious" designs, where the license fee is a drop in
the bucket compared to part sales.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

On Aug 15, 1:37=A0pm, MarkAren <markare...@yahoo.com> wrote:
> Hi All,
>
> I have just compiled a NIOS II core into Cyclone I part (I was given
> an old MJL demo board) and compiled some trivial C. Everything seems
> to work as advertised.
>
> I still haven't figured out the time limited nature of the NIOS II
> SOPC builder, could someone enlighten me please. There seems to be a
> 60 minute limit between creating the FPGA code (Verilog) and compiling
> a new FPGA image, or does that limit apply to time between compiling
> an image and programming a part ?
>
> Also, what is the difference between the web edition and the fully
> paid up version of Quartus II.
>
> All tools above are V7.2.
>
> I am only experimenting at the moment and I need to understand the
> limitations of the tool chain before I invest too much more time and
> effort in this educational project,.
>
> Many thanks,
>
> Mark

As I recall, the time limit starts after downloading the FPGA.

I was told that the difference between 'web' and 'full' was the number
(size) of devices supported.

I'm pretty sure that all of this is documented on the Altera web site.

G.

On Aug 16, 9:53=A0am, ghelbig <ghel...@lycos.com> wrote:
> On Aug 15, 1:37=A0pm, MarkAren <markare...@yahoo.com> wrote:
>
>
>
>
>
> > Hi All,
>
> > I have just compiled a NIOS II core into Cyclone I part (I was given
> > an old MJL demo board) and compiled some trivial C. Everything seems
> > to work as advertised.
>
> > I still haven't figured out the time limited nature of the NIOS II
> > SOPC builder, could someone enlighten me please. There seems to be a
> > 60 minute limit between creating the FPGA code (Verilog) and compiling
> > a new FPGA image, or does that limit apply to time between compiling
> > an image and programming a part ?
>
> > Also, what is the difference between the web edition and the fully
> > paid up version of Quartus II.
>
> > All tools above are V7.2.
>
> > I am only experimenting at the moment and I need to understand the
> > limitations of the tool chain before I invest too much more time and
> > effort in this educational project,.
>
> > Many thanks,
>
> > Mark
>
> As I recall, the time limit starts after downloading the FPGA.
>
> I was told that the difference between 'web' and 'full' was the number
> (size) of devices supported.
>
> I'm pretty sure that all of this is documented on the Altera web site.
>
> G.- Hide quoted text -
>
> - Show quoted text -

Hi Guys,

Thanks for the comments so far.

I agree that US$600 is a load of money for the hobbyist, but this is
one hell of a useful tool from where I sit.

So as far as the JTAG download session being valid for 60 minutes,
that makes sense.

What if one was to burn the image into FLASH then use another device
to download the configuration using AS or PS formats ?

I assume that the timeout mechanism is within the FPGA, so this won't
work (unless the design reboots itself every 58 minutes ?)

Comments please.

Thanks,

Mark