need fast FPGA suggestions

Andrew FPGA wrote:

>>So, you think a 13-bit counter feeding a 13-bit identity comparator will
>>work at 250 MHz?
> 
> Others have said it may be possible but what they fail to acknowledge
> is the large amount of extra design effort and care required to get
> there. 250 MHz is really pushing the limits in spartan 3e in my
> experience. You may have to work very hard to get there: for example I
> have just finished a distributed arithmetic filter design, that has
> only 1 LUT level between flops and after a lot of effort I got it to
> run at 206 MHz in a sp3 1600e. I can see how to get to 220MHz, but
> beyond that I don't know. The longest carry chain is 10 bits.
> 
> I had to bypass synthesis and instantiate xilinx primitives directly
> to gaurantee my logic was implemented in 1 LUT level. Then I had to
> manually floorplan the design - placing each flop with the
> corresponding LUT by hand( I uses RLOC's embedded in the VHDL source).
> The automatic placer didn't always place the LUT with the FLOP so you
> end up with 2 routes which kills the timing completely.
> 
> 
>>Yeah, I really don't think we can handle $2000 IC's.  This isn't a real
>>production project, we might build 5 of them at a time, but we are still
>>cost-sensitive.
> 
> If its such low volumes just take the unit cost hit and move to a
> Virtex part. How valuable is your time?

I agree.  250 MHz is really pushing it in a Spartan3, especially if 
there are any carry chains involved.  Unless you have the volume where 
material costs are going to swamp your development costs, move up to a 
V4 or V5.  If the volume is low, just use one of the evaluation boards 
and save yourself a lot of board development effort.

Jon Elson wrote:
(snip)

> Well, it is all designed and the board is layed out.  I used the AD 
> CMP603 single fast comparator.  A bear to mount, but a very fine chip 
> for the purpose.  It DOES use 2 range switching caps, plus stray 
> capacitance as the lowest cap value, plus 2 selections of 
> current-programming resistor.

One that I worked on some time ago, using a custom ASIC, did
something like that for the low order bits and digital counter
logic for the high bits.  The goal was to measure the arrival time
of pulses fairly accurately.

As for fully digital, it might be that you could use four 125MHz
clocks 90 degrees apart in phase, and for input timing latch the
input with all four clocks.  For output, OR the output of four
registers, each clocked by one of the clocks, with the appropriate
input depending on which edge it should switch.

There are many other design methods which trade more slow logic
for a small amount of fast logic.

Otherwise, a small amount of ECL on the output of the FPGA and
before the real output could do it.  For example, put a small
loadable ECL shift register on the output of the FPGA, clocked
at the full 500MHz, but the FPGA clocks much slower.
(How fast is ECL these days?)

-- glen

On Sat, 13 Sep 2008 23:32:47 -0800
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

> Jon Elson wrote:
> (snip)
> 
> > Well, it is all designed and the board is layed out.  I used the AD 
> > CMP603 single fast comparator.  A bear to mount, but a very fine chip 
> > for the purpose.  It DOES use 2 range switching caps, plus stray 
> > capacitance as the lowest cap value, plus 2 selections of 
> > current-programming resistor.
> 
> One that I worked on some time ago, using a custom ASIC, did
> something like that for the low order bits and digital counter
> logic for the high bits.  The goal was to measure the arrival time
> of pulses fairly accurately.
> 
> As for fully digital, it might be that you could use four 125MHz
> clocks 90 degrees apart in phase, and for input timing latch the
> input with all four clocks.  For output, OR the output of four
> registers, each clocked by one of the clocks, with the appropriate
> input depending on which edge it should switch.
> 
> There are many other design methods which trade more slow logic
> for a small amount of fast logic.
> 
> Otherwise, a small amount of ECL on the output of the FPGA and
> before the real output could do it.  For example, put a small
> loadable ECL shift register on the output of the FPGA, clocked
> at the full 500MHz, but the FPGA clocks much slower.
> (How fast is ECL these days?)
> 
> -- glen
> 

EP51 D-flop claims 320ps typ clock to out, 3GHz maximum toggle frequency.  Which I suppose is fast enough for some people.  You know, the ones doing pedestrian stuff.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Rob Gaddi wrote:
>>
> 
> EP51 D-flop claims 320ps typ clock to out, 3GHz maximum toggle frequency.  Which I suppose is fast enough for some people.  You know, the ones doing pedestrian stuff.
> 

Assuming 0 pS of routing for the Q to CLK pin that would give you a 
320pS High and Low times for a total period of 640pS or 1.5625 GHz.

Ed

On Aug 26, 8:53=A0am, "Robert F. Jarnot" <Robert.F.Jar...@jpl.nasa.gov>
wrote:
> Glenn,
>
> =A0 =A0 =A0 =A0 I have tried hard to get data on the Achronix parts, but =
have never
> succeeded in obtaining any useful/detailed information at all, nor have
> I ever received any kind of a response from the company when requesting
> information. =A0Have you come across a source of substantive data on thes=
e
> mysterious devices?

I just went there and the data sheet has a revision of Sep 15
(yesterday!).

That must be the "hottest" data sheet I have ever seen (in more than
one sense).

Very interesting technology, can't wait to hear more about it.

Tommy