Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?

Hi,

I wrote a dual-port ram model according to xst example, it should be
inferred to a dual-port block ram with both ports writable at the same
time but different addresses. However, I got an error msg - "You are
apparently trying to describe a RAM with several write ports for
signal <x>. This RAM cannot be implemented using distributed
resources." Any hints what might have gone wrong? thanks,

always @ (posedge clk)
 if(ena)
   begin
    if(wea)
      mem[addra] <= dia;
    doa<=mem[addra];
   end

always @ (posedge clk)
 if(enb)
   begin
    if(web)
      mem[addrb] <= dib;
    dob<=mem[addrb];
   end

jack.harvard@googlemail.com wrote:
> Hi,
> 
> I wrote a dual-port ram model according to xst example, it should be
> inferred to a dual-port block ram with both ports writable at the same
> time but different addresses. However, I got an error msg - "You are
> apparently trying to describe a RAM with several write ports for
> signal <x>. This RAM cannot be implemented using distributed
> resources." Any hints what might have gone wrong? thanks,
> 
> always @ (posedge clk)
>  if(ena)
>    begin
>     if(wea)
>       mem[addra] <= dia;
>     doa<=mem[addra];
>    end
> 
> always @ (posedge clk)
>  if(enb)
>    begin
>     if(web)
>       mem[addrb] <= dib;
>     dob<=mem[addrb];
>    end

Have you used an attribute (or directive) to help the synthesizer 
realize you want BlockRAM rather than distributed RAM?

You haven't mentioned the synthesizer.

On Sep 2, 2:07=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
> jack.harv...@googlemail.com wrote:
> > Hi,
>
> > I wrote a dual-port ram model according to xst example, it should be
> > inferred to a dual-port block ram with both ports writable at the same
> > time but different addresses. However, I got an error msg - "You are
> > apparently trying to describe a RAM with several write ports for
> > signal <x>. This RAM cannot be implemented using distributed
> > resources." Any hints what might have gone wrong? thanks,
>
> > always @ (posedge clk)
> > =A0if(ena)
> > =A0 =A0begin
> > =A0 =A0 if(wea)
> > =A0 =A0 =A0 mem[addra] <=3D dia;
> > =A0 =A0 doa<=3Dmem[addra];
> > =A0 =A0end
>
> > always @ (posedge clk)
> > =A0if(enb)
> > =A0 =A0begin
> > =A0 =A0 if(web)
> > =A0 =A0 =A0 mem[addrb] <=3D dib;
> > =A0 =A0 dob<=3Dmem[addrb];
> > =A0 =A0end
>
> Have you used an attribute (or directive) to help the synthesizer
> realize you want BlockRAM rather than distributed RAM?
>
> You haven't mentioned the synthesizer.

Yes, if (* bram_map=3D"yes" *) should do?

On Sep 2, 6:48=A0am, "jack.harv...@googlemail.com"
<jack.harv...@googlemail.com> wrote:
> On Sep 2, 2:07=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
>
> > Have you used an attribute (or directive) to help the synthesizer
> > realize you want BlockRAM rather than distributed RAM?
>
> > You haven't mentioned the synthesizer.
>
> Yes, if (* bram_map=3D"yes" *) should do

The attribute says "XST" so...

Two suggestions:  first try
  (* BRAM_MAP=3D"yes" *)

Second, try to use the syntax explicitly defined in the Xilinx
reference:

http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0054_15.htm=
l

The message you got suggests to me it was trying to used distributed
memory and the BRAM_MAP attribute didn't "take."

On Tue, 2 Sep 2008 05:24:00 -0700 (PDT), "jack.harvard@googlemail.com"
<jack.harvard@googlemail.com> wrote:

>Hi,
>
>I wrote a dual-port ram model according to xst example, it should be
>inferred to a dual-port block ram with both ports writable at the same
>time but different addresses. However, I got an error msg - "You are
>apparently trying to describe a RAM with several write ports for
>signal <x>. This RAM cannot be implemented using distributed
>resources." Any hints what might have gone wrong? thanks,

Focus on this: "This RAM cannot be implemented using distributed
resources".
There is apparently something about your template (or its interaction
with XST) that prevents this RAM being mapped into BlockRams.

I can't help with details, I don't do Verilog. But search for DPRAM
template examples that do work, or try some basic variations, e.g.
combining both "if" clauses into the same clocked process,  or assigning
doa<=dia inside the write clause, to see if you can get past this block.

- Brian

On Sep 3, 1:10=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Tue, 2 Sep 2008 05:24:00 -0700 (PDT), "jack.harv...@googlemail.com"
>
> <jack.harv...@googlemail.com> wrote:
> >Hi,
>
> >I wrote a dual-port ram model according to xst example, it should be
> >inferred to a dual-port block ram with both ports writable at the same
> >time but different addresses. However, I got an error msg - "You are
> >apparently trying to describe a RAM with several write ports for
> >signal <x>. This RAM cannot be implemented using distributed
> >resources." Any hints what might have gone wrong? thanks,
>
> Focus on this: "This RAM cannot be implemented using distributed
> resources".
> There is apparently something about your template (or its interaction
> with XST) that prevents this RAM being mapped into BlockRams.
>
> I can't help with details, I don't do Verilog. But search for DPRAM
> template examples that do work, or try some basic variations, e.g.
> combining both "if" clauses into the same clocked process, =A0or assignin=
g
> doa<=3Ddia inside the write clause, to see if you can get past this block=
.
>
> - Brian

It looks that a "feature" of XST, the template won't be synthesized to
dual-port rams with both writes
http://www.xilinx.com/support/answers/22385.htm
No matter how I try.

=3D=3D=3DFrom Xilinx=3D=3D=3D
Dual-port RAM support is only for Virtex-2 Pro families and newer, and
is not intended for older devices. If you target one of the newer
devices, the correct type of RAM is inferred.

To work around the issue, you can either instantiate the block RAM
primitive that you want to use, or use CORE Generator to generate the
RAM.

On Sep 3, 7:21=A0am, "jack.harv...@googlemail.com"
<jack.harv...@googlemail.com> wrote:
<snip>
> Dual-port RAM support is only for Virtex-2 Pro families and newer, and
> is not intended for older devices. If you target one of the newer
> devices, the correct type of RAM is inferred.
<snip>

What device are you working with?  V2Pro is getting a bit long in the
tooth by now.

On 3 Sep, 16:54, John_H <newsgr...@johnhandwork.com> wrote:
> On Sep 3, 7:21=A0am, "jack.harv...@googlemail.com"<jack.harv...@googlemai=
l.com> wrote:
>
> <snip>> Dual-port RAM support is only for Virtex-2 Pro families and newer=
, and
> > is not intended for older devices. If you target one of the newer
> > devices, the correct type of RAM is inferred.
>
> <snip>
>
> What device are you working with? =A0V2Pro is getting a bit long in the
> tooth by now.

It's a Spartan3A.

On Wed, 3 Sep 2008 09:18:32 -0700 (PDT), "jack.harvard@googlemail.com"
<jack.harvard@googlemail.com> wrote:

>On 3 Sep, 16:54, John_H <newsgr...@johnhandwork.com> wrote:
>> On Sep 3, 7:21&#4294967295;am, "jack.harv...@googlemail.com"<jack.harv...@googlemail.com> wrote:
>>
>> <snip>> Dual-port RAM support is only for Virtex-2 Pro families and newer, and
>> > is not intended for older devices. If you target one of the newer
>> > devices, the correct type of RAM is inferred.
>>
>> <snip>
>>
>> What device are you working with? &#4294967295;V2Pro is getting a bit long in the
>> tooth by now.
>
>It's a Spartan3A.

Which is younger than the V2Pro.
The AR# you gave referred to the Spartan-2 family.
You may still be in luck.

But it's only worth pushing on that rope for so long. Then concede
defeat; save time and instantiate the primitive component directly.

- Brian

Brian Drummond wrote:

> But it's only worth pushing on that rope for so long. Then concede
> defeat; save time and instantiate the primitive component directly.

Or use the portable template with one read and one write port.

        -- Mike Treseler