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Spartan-3 -> Spartan-2 problem

Started by aleksa September 4, 2008
About two months ago I've started learning VHDL, CPLD and FPGA.

Right from the start I've choosen Spartan-3 (XC3S50) and
didn't look at Spartan-II because I wanted to use the latest chip.

Now I am making a board with 50 5V TTL inputs and idea was to use
the CPLD XC95144XL as a level translator...but I just don't like it.

So, now I am trying Spartan-II (XC2S50),
which is 5V tolerant, and I have 3 problems/issues:

1. when I start "Implement design", ISE complains:
   "MapLib:95 - IBUF symbol "CLOCK1_IBUF" (output signal=CLOCK1_IBUF1)
    is promoted to indicate the use of GCLKIOB site."

   I have 7 clocks in my design and ISE gives me the same report
   for 3 of them. What does it mean and what should I do about it?

   It works fine on spartan-3.


2. when I start "Floorplan IO - Pre-Synthesis", ISE complains:
   "ERROR:HDLParsers:3562 - pepExtractor.prj line 1
    Expecting 'vhdl' or 'verilog'   keyword,  found 'work'."

   (This I can fix with LOC attribute..)


3. for how long will	 Spartan-II be available?


Cheers