Signed multiplication

hi

Can anyone tell me how can i multiply two signed numbers in FPGA.
How the logic is really implemented..
ie., if i multiply two signed numbers are they multiplying the
positive number and the 2's complement (if the number is negative)
directly ..?
Or are they really changing the negative number to positive and do
normal multiplication and appends the sign accordingly..?
And is the positive number, and its 2's complement form same always...?

>hi
>
>Can anyone tell me how can i multiply two signed numbers in FPGA.
>How the logic is really implemented..
>ie., if i multiply two signed numbers are they multiplying the
>positive number and the 2's complement (if the number is negative)
>directly ..?
>Or are they really changing the negative number to positive and do
>normal multiplication and appends the sign accordingly..?
>And is the positive number, and its 2's complement form same always...?
>

It depends on the FPGA and the way you specify the multiplication
operation.

If it uses a hardware "DSP" or "MAC" resource, the logic internal to that
block will know what to do with the sign bits.

Otherwise, the synthesis tool will know how to handle the bits if, for
instance, you are writing in VHDL and declare the signals to be of type
'signed'.

What FPGA are you using?
What language are you writing in?
Why don't you do some experiments and look at the log files and gate-level
netlist?
Have you tried multiplying -1 x -1?

On Sun, 7 Sep 2008 23:10:31 -0700 (PDT), knight <krsheshu@gmail.com>
wrote:

>hi
>
>Can anyone tell me how can i multiply two signed numbers in FPGA.
>How the logic is really implemented..
>ie., if i multiply two signed numbers are they multiplying the
>positive number and the 2's complement (if the number is negative)
>directly ..?
>Or are they really changing the negative number to positive and do
>normal multiplication and appends the sign accordingly..?
>And is the positive number, and its 2's complement form same always...?

If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5)
for most FPGAs you just use the * operator and expect the tools to use
the in-built multipliers.

For more details, read the documentation on these multiplier or DSP48
blocks.

For larger operators, this works well enough as long as you don't need
the highest achevable speeds (maybe this is fixed in ISE 10?).

But if you are "rolling your own" multiplier (perhaps to get a properly
pipelined 32*32 multiplier for speed, using the internal components) the
easiest way is to convert to unsigned numbers, and handle the sign bits
separately.

- Brian

On 8 Sep, 07:10, knight <krshe...@gmail.com> wrote:
> hi
>
> Can anyone tell me how can i multiply two signed numbers in FPGA.
> How the logic is really implemented..
> ie., if i multiply two signed numbers are they multiplying the
> positive number and the 2's complement (if the number is negative)
> directly ..?
> Or are they really changing the negative number to positive and do
> normal multiplication and appends the sign accordingly..?
> And is the positive number, and its 2's complement form same always...?

How many bits of the result do you need? If you only need the same
number of output bits as input, I don't think it matters whether the
numbers are signed or unsigned.

Jon

On Sep 8, 7:14=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Sun, 7 Sep 2008 23:10:31 -0700 (PDT), knight <krshe...@gmail.com>
> wrote:
>
> >hi
>
> >Can anyone tell me how can i multiply two signed numbers in FPGA.
> >How the logic is really implemented..
> >ie., if i multiply two signed numbers are they multiplying the
> >positive number and the 2's complement (if the number is negative)
> >directly ..?
> >Or are they really changing the negative number to positive and do
> >normal multiplication and appends the sign accordingly..?
> >And is the positive number, and its 2's complement form same always...?
>
> If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5)
> for most FPGAs you just use the * operator and expect the tools to use
> the in-built multipliers.
>
> For more details, read the documentation on these multiplier or DSP48
> blocks.
>
> For larger operators, this works well enough as long as you don't need
> the highest achevable speeds (maybe this is fixed in ISE 10?).
>
> But if you are "rolling your own" multiplier (perhaps to get a properly
> pipelined 32*32 multiplier for speed, using the internal components) the
> easiest way is to convert to unsigned numbers, and handle the sign bits
> separately.

I wouldn't agree with that last suggestion.  This takes extra logic in
the data path to complement the numbers, both on input and output.
The Booths algorithm can multiply signed inputs and works as well as
unsigned multiplies.

Rick

On Sep 8, 7:35=A0am, Jon Beniston <j...@beniston.com> wrote:
> On 8 Sep, 07:10, knight <krshe...@gmail.com> wrote:
>
> > hi
>
> > Can anyone tell me how can i multiply two signed numbers in FPGA.
> > How the logic is really implemented..
> > ie., if i multiply two signed numbers are they multiplying the
> > positive number and the 2's complement (if the number is negative)
> > directly ..?
> > Or are they really changing the negative number to positive and do
> > normal multiplication and appends the sign accordingly..?
> > And is the positive number, and its 2's complement form same always...?
>
> How many bits of the result do you need? If you only need the same
> number of output bits as input, I don't think it matters whether the
> numbers are signed or unsigned.
>
> Jon

Well. . .

Most people want the most significant portion of the result, even if
they
only need the same number of bits output as input.  So although the
low 8 bits of 8 x 8 signed multiply and 8 x 8 unsigned multiply are
the
same, the high 8 bits are certainly not the same.  For example if you
have hex FF (255 unsigned or -1 signed) the output of the unsigned
multiplier will be hex FE01, while the output of the signed multiplier
will be 0001.

Regards,
Gabor

> Most people want the most significant portion of the result, even if
> they only need the same number of bits output as input.

I'm not sure I agree with that. Maybe if you're doing fractional
arithmetic, but not for integer.

>=A0So although the
> low 8 bits of 8 x 8 signed multiply and 8 x 8 unsigned multiply are
> the
> same, the high 8 bits are certainly not the same. =A0For example if you
> have hex FF (255 unsigned or -1 signed) the output of the unsigned
> multiplier will be hex FE01, while the output of the signed multiplier
> will be 0001.

True - what I said is only valid if you're only interested in the
lower bits. So just make sure you first sign extend to the number of
bits you want if you take this approach.

Jon

knight <krsheshu@gmail.com> writes:
> Can anyone tell me how can i multiply two signed numbers in FPGA.
> How the logic is really implemented..

There are many possible methods; one of the simplest but not
necessarily the highest performance is a Baugh-Wooley multiplier.
Google turns up some references, but for a good explanation you'd have
to find a book on digital arithmetic.

On Mon, 8 Sep 2008 06:40:38 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:

>On Sep 8, 7:14&#4294967295;am, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:

>> But if you are "rolling your own" multiplier (perhaps to get a properly
>> pipelined 32*32 multiplier for speed, using the internal components) the
>> easiest way is to convert to unsigned numbers, and handle the sign bits
>> separately.
>
>I wouldn't agree with that last suggestion.  This takes extra logic in
>the data path to complement the numbers, both on input and output.
>The Booths algorithm can multiply signed inputs and works as well as
>unsigned multiplies.

Good point. My approach probably isn't the optimal solution in terms of
gate count, if space is tight.

Can you really use Booths algorithm for decomposing a large signed
multiplication into 18*18 blocks? I have only seen it used at the level
of individual additions/subtractions. I haven't really considered using
it over the built-in mults/DSP48s. If that works, it would certainly be
a better approach.

- Brian

Brian Drummond wrote:
> 
> If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5)
> for most FPGAs you just use the * operator and expect the tools to use
> the in-built multipliers.
> 
> For more details, read the documentation on these multiplier or DSP48
> blocks.
> 
> For larger operators, this works well enough as long as you don't need
> the highest achevable speeds (maybe this is fixed in ISE 10?).

If you follow the multiply with several plain old register stages, the 
synthesis tool will properly absorb the registers into a pipelined 
structure (at least, XST with ISE9 will).