On Sep 23, 12:55=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote:> On Mon, 22 Sep 2008 11:51:29 -0700 (PDT), osquillar > > <ogm101...@hotmail.com> wrote: > >> > > > Hello all, I'm working with an microblaze system and I'm trying =to> >> > > > work with a Micron MT48LC16M16 memory and something strange happ=ens,> >> > > > It seem than I can read positions all position but if I try to w=rite> >> > > > in positions 00 and 01 nothing changes and if I write something =in> >> > > > positions 02 and 03 they seems to be written in position 00 and =01. It> >> > > > happens the same with the rest of the memory. > >ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > >DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 > > >If I read the result after writting. > > >ADDRESS =A0 =A0 =A0 =A000 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F > >DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 > > What result did you get in simulation? > > - BrianHello Brian, I did not simulate it.
SDRAM question
Started by ●September 17, 2008
Reply by ●September 24, 20082008-09-24
Reply by ●September 24, 20082008-09-24
On Wed, 24 Sep 2008 00:25:55 -0700 (PDT), osquillar <ogm101274@hotmail.com> wrote:>On Sep 23, 12:55�pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Mon, 22 Sep 2008 11:51:29 -0700 (PDT), osquillar >> >> <ogm101...@hotmail.com> wrote: >> >> > > > Hello all, I'm working with an microblaze system and I'm trying to >> >> > > > work with a Micron MT48LC16M16 memory and something strange happens, >> >> > > > It seem than I can read positions all position but if I try to write >> >> > > > in positions 00 and 01 nothing changes and if I write something in >> >> > > > positions 02 and 03 they seems to be written in position 00 and 01. It >> >> > > > happens the same with the rest of the memory. >> >ADDRESS � � � �00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >> >DATA WRITTEN 01 23 45 67 89 AB CD EF 11 22 33 44 55 66 77 88 >> >> >If I read the result after writting. >> >> >ADDRESS � � � �00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F >> >DATA WRITTEN 45 67 FA DE CD EF 25 27 33 44 DA 11 77 88 FE A2 >> >> What result did you get in simulation? >> >> - Brian > >Hello Brian, I did not simulate it.That makes it unnecessarily hard to find the problem, which looks like a pipeline error of some kind, such as data being presented to the memory a cycle or two late, or an unintended pipeline stage in the read path. Micron publish simulation models for their devices. Unfortunately, no longer in VHDL, but depending on your simulator you may be able to use the Verilog models they publish. Some Modelsim licences allow mixed language simulation. Also the ISE simulator (in ISE 10) allows it in theory, but in practice you have to find a workaround for a crash. If you are using Modelsim you can find the equivalent Hynix part; Hynix publish VHDL models, but only precompiled for Modelsim... - Brian
