Is it possible to get an RTL netlist from Xilinx tools?

Hello everyone,

I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
because it's so slow and cumbersome to use.  What I'd like to do is
output a netlist and use another script to process that netlist into
input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).

I have figured out how to get the Xilinx tools to output a netlist,
but it appears they output a 'technology' version and not an 'RTL'
version of the netlist.

Is there any way to get the tools to output a netlist that is in the
more useful (to me) 'RTL' format?

My desire is to be able to write VHDL code, build it with my build
process and check the RTL without ever having to enter Xilinx's IDE.
I'd also like to be able to easily extract schematics for inclusion
into the chronicle of my personal project at
http://www.harp-project.com/, but the Xilnix tools make this
incredibly difficult.

Thanks for any info,
thutt

thutt wrote:
> Hello everyone,
> 
> I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
> because it's so slow and cumbersome to use.  What I'd like to do is
> output a netlist and use another script to process that netlist into
> input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
> 
> I have figured out how to get the Xilinx tools to output a netlist,
> but it appears they output a 'technology' version and not an 'RTL'
> version of the netlist.
> 
> Is there any way to get the tools to output a netlist that is in the
> more useful (to me) 'RTL' format?
> 
> My desire is to be able to write VHDL code, build it with my build
> process and check the RTL without ever having to enter Xilinx's IDE.
> I'd also like to be able to easily extract schematics for inclusion
> into the chronicle of my personal project at
> http://www.harp-project.com/, but the Xilnix tools make this
> incredibly difficult.
> 
> Thanks for any info,
> thutt
> 
I think the RTL schematic is in a proprietary format.  I don't know if 
it's possible to view it in another tool.  If you want a better viewer 
for the technology schematic, you can import the NGC into PlanAhead, 
which now comes with ISE.  If you want a better RTL viewer, you probably 
have to resynthesize with a different synthesizer and view the schematic 
in that tool.  -Kevin

Kevin Neilson <kevin_neilson@removethiscomcast.net> writes:

> thutt wrote:
> > Hello everyone,
> > I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
> > because it's so slow and cumbersome to use.  What I'd like to do is
> > output a netlist and use another script to process that netlist into
> > input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
> > I have figured out how to get the Xilinx tools to output a netlist,
> > but it appears they output a 'technology' version and not an 'RTL'
> > version of the netlist.
> > Is there any way to get the tools to output a netlist that is in the
> > more useful (to me) 'RTL' format?
> > My desire is to be able to write VHDL code, build it with my build
> > process and check the RTL without ever having to enter Xilinx's IDE.
> > I'd also like to be able to easily extract schematics for inclusion
> > into the chronicle of my personal project at
> > http://www.harp-project.com/, but the Xilnix tools make this
> > incredibly difficult.
> > Thanks for any info,
> > thutt
> >
> I think the RTL schematic is in a proprietary format.  I don't know if
> it's possible to view it in another tool.  If you want a better viewer
> for the technology schematic, you can import the NGC into PlanAhead,
> which now comes with ISE.  If you want a better RTL viewer, you
> probably have to resynthesize with a different synthesizer and view
> the schematic in that tool.  -Kevin

I don't understand how the RTL can be in a proprietary format, if I'm
reading the technology schematic correctly.  As far as I can tell,
each LUT in the technology schematic represents some level of
'complex' logic which can be viewed in RTL form by double clicking on
the LUT in the technology schematic viewer.

Each LUT also has an associated initialization value, a 16-bit
hexadecimal number; I assume that the initialization value is the key
which turns the lock and causes the LUT to implement a certain
functionality.

If that's the case, has anyone spent the time to figure out the
mappings of initialization codes to LUT implementations?  Or, does
Xilinx publish this information?  (I seem to recall a post in either
this newsgroup or comp.lang.vhdl which described how this was derived,
but I don't recall if it went into any specificity with regards to
Xilinx initialization values).

If there were a lookup table of initialization values to the standard
'and / or / xor'-type logic that each represents, then it would be
quite possible to write a script to make an external RTL viewer based
on the technology netlist output by the Xilinx tools.

Anyone game for a little sleuthing to determine all the LUT init
codes?

thutt
-- 
I have never met a beet which I like.

thutt wrote:
> Kevin Neilson <kevin_neilson@removethiscomcast.net> writes:
> 
>> thutt wrote:
>>> Hello everyone,
>>> I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
>>> because it's so slow and cumbersome to use.  What I'd like to do is
>>> output a netlist and use another script to process that netlist into
>>> input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
>>> I have figured out how to get the Xilinx tools to output a netlist,
>>> but it appears they output a 'technology' version and not an 'RTL'
>>> version of the netlist.
>>> Is there any way to get the tools to output a netlist that is in the
>>> more useful (to me) 'RTL' format?
>>> My desire is to be able to write VHDL code, build it with my build
>>> process and check the RTL without ever having to enter Xilinx's IDE.
>>> I'd also like to be able to easily extract schematics for inclusion
>>> into the chronicle of my personal project at
>>> http://www.harp-project.com/, but the Xilnix tools make this
>>> incredibly difficult.
>>> Thanks for any info,
>>> thutt
>>>
>> I think the RTL schematic is in a proprietary format.  I don't know if
>> it's possible to view it in another tool.  If you want a better viewer
>> for the technology schematic, you can import the NGC into PlanAhead,
>> which now comes with ISE.  If you want a better RTL viewer, you
>> probably have to resynthesize with a different synthesizer and view
>> the schematic in that tool.  -Kevin
> 
> I don't understand how the RTL can be in a proprietary format, if I'm
> reading the technology schematic correctly.  As far as I can tell,
> each LUT in the technology schematic represents some level of
> 'complex' logic which can be viewed in RTL form by double clicking on
> the LUT in the technology schematic viewer.
> 
> Each LUT also has an associated initialization value, a 16-bit
> hexadecimal number; I assume that the initialization value is the key
> which turns the lock and causes the LUT to implement a certain
> functionality.
> 
> If that's the case, has anyone spent the time to figure out the
> mappings of initialization codes to LUT implementations?  Or, does
> Xilinx publish this information?  (I seem to recall a post in either
> this newsgroup or comp.lang.vhdl which described how this was derived,
> but I don't recall if it went into any specificity with regards to
> Xilinx initialization values).
> 
> If there were a lookup table of initialization values to the standard
> 'and / or / xor'-type logic that each represents, then it would be
> quite possible to write a script to make an external RTL viewer based
> on the technology netlist output by the Xilinx tools.
> 
> Anyone game for a little sleuthing to determine all the LUT init
> codes?
>

It's a bit harder than that. Assume a LUT has 4 inputs (it varies
with different FPGA families). The synthesiser (eg XST) will look for a
piece of combinatorial logic with 4 inputs & 1 output. It then simulates
that logic, evaluating its output for all 16 possible input
combinations. The initialisation string is simply the map of those 16
outputs, written out in hex.
So there really isn't an underlying logic representation: the designer
might have specified any Boolean function whatever (adder, parity tree,
etc): the synthesiser doesn't care.

On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote:

>
>Hello everyone,
>
>I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
>because it's so slow and cumbersome to use.  What I'd like to do is
>output a netlist and use another script to process that netlist into
>input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
>
>I have figured out how to get the Xilinx tools to output a netlist,
>but it appears they output a 'technology' version and not an 'RTL'
>version of the netlist.

>Is there any way to get the tools to output a netlist that is in the
>more useful (to me) 'RTL' format?

Have you looked at the post-synthesis simulation model (in VHDL)?

- Brian

Brian Drummond <brian_drummond@btconnect.com> writes:

> On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote:
> 
> >
> >Hello everyone,
> >
> >I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
> >because it's so slow and cumbersome to use.  What I'd like to do is
> >output a netlist and use another script to process that netlist into
> >input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
> >
> >I have figured out how to get the Xilinx tools to output a netlist,
> >but it appears they output a 'technology' version and not an 'RTL'
> >version of the netlist.
> 
> >Is there any way to get the tools to output a netlist that is in the
> >more useful (to me) 'RTL' format?
> 
> Have you looked at the post-synthesis simulation model (in VHDL)?
> 
> - Brian

No.  Why?

I don't understand; I'm not looking to simulate, I'm looking to view a
schematic outside of ISE.

-- 
Hot glass looks just like cold glass.

David R Brooks wrote:

> thutt wrote:
> 
>>Kevin Neilson <kevin_neilson@removethiscomcast.net> writes:
>>
>>
>>>thutt wrote:
>>>
>>>>Hello everyone,
>>>>I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
>>>>because it's so slow and cumbersome to use.  What I'd like to do is
>>>>output a netlist and use another script to process that netlist into
>>>>input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
>>>>I have figured out how to get the Xilinx tools to output a netlist,
>>>>but it appears they output a 'technology' version and not an 'RTL'
>>>>version of the netlist.
>>>>Is there any way to get the tools to output a netlist that is in the
>>>>more useful (to me) 'RTL' format?
>>>>My desire is to be able to write VHDL code, build it with my build
>>>>process and check the RTL without ever having to enter Xilinx's IDE.
>>>>I'd also like to be able to easily extract schematics for inclusion
>>>>into the chronicle of my personal project at
>>>>http://www.harp-project.com/, but the Xilnix tools make this
>>>>incredibly difficult.
>>>>Thanks for any info,
>>>>thutt
>>>>
>>>
>>>I think the RTL schematic is in a proprietary format.  I don't know if
>>>it's possible to view it in another tool.  If you want a better viewer
>>>for the technology schematic, you can import the NGC into PlanAhead,
>>>which now comes with ISE.  If you want a better RTL viewer, you
>>>probably have to resynthesize with a different synthesizer and view
>>>the schematic in that tool.  -Kevin
>>
>>I don't understand how the RTL can be in a proprietary format, if I'm
>>reading the technology schematic correctly.  As far as I can tell,
>>each LUT in the technology schematic represents some level of
>>'complex' logic which can be viewed in RTL form by double clicking on
>>the LUT in the technology schematic viewer.
>>
>>Each LUT also has an associated initialization value, a 16-bit
>>hexadecimal number; I assume that the initialization value is the key
>>which turns the lock and causes the LUT to implement a certain
>>functionality.
>>
>>If that's the case, has anyone spent the time to figure out the
>>mappings of initialization codes to LUT implementations?  Or, does
>>Xilinx publish this information?  (I seem to recall a post in either
>>this newsgroup or comp.lang.vhdl which described how this was derived,
>>but I don't recall if it went into any specificity with regards to
>>Xilinx initialization values).
>>
>>If there were a lookup table of initialization values to the standard
>>'and / or / xor'-type logic that each represents, then it would be
>>quite possible to write a script to make an external RTL viewer based
>>on the technology netlist output by the Xilinx tools.
>>
>>Anyone game for a little sleuthing to determine all the LUT init
>>codes?
>>
> 
> 
> It's a bit harder than that. Assume a LUT has 4 inputs (it varies
> with different FPGA families). The synthesiser (eg XST) will look for a
> piece of combinatorial logic with 4 inputs & 1 output. It then simulates
> that logic, evaluating its output for all 16 possible input
> combinations. The initialisation string is simply the map of those 16
> outputs, written out in hex.
> So there really isn't an underlying logic representation: the designer
> might have specified any Boolean function whatever (adder, parity tree,
> etc): the synthesiser doesn't care.
> 
The actual LUT is a 16x1 memory so the sixteen bits are the memory
contents.  As stated in the answer above, the original logic has been
compressed and is not available.

thutt wrote:
> Kevin Neilson <kevin_neilson@removethiscomcast.net> writes:
> 
>> thutt wrote:
..snip..
> 
> Each LUT also has an associated initialization value, a 16-bit
> hexadecimal number; I assume that the initialization value is the key
> which turns the lock and causes the LUT to implement a certain
> functionality.
> 
> If that's the case, has anyone spent the time to figure out the
> mappings of initialization codes to LUT implementations?  Or, does
> Xilinx publish this information?  (I seem to recall a post in either
> this newsgroup or comp.lang.vhdl which described how this was derived,
> but I don't recall if it went into any specificity with regards to
> Xilinx initialization values).
> 
> If there were a lookup table of initialization values to the standard
> 'and / or / xor'-type logic that each represents, then it would be
> quite possible to write a script to make an external RTL viewer based
> on the technology netlist output by the Xilinx tools.
> 
> Anyone game for a little sleuthing to determine all the LUT init
> codes?

There is nothing secret at all about the LUT INIT values.  A LUT4 has a 
INIT[3:0] string representing 16 values (2^4) where inputs I0=0, I1=1, 
I2=2, and I3=3 or otherwise written as INIT[{I3,I2,I1,I0}].  It is 
trivial to convert the truth table to a boolean equation using a 
Karnaugh map http://en.wikipedia.org/wiki/Karnaugh_map

A LUT5 and LUT6 operate in the same way, just with 5 and 6 bit strings.

Ed McGettigan
--
Xilinx Inc.

thutt wrote:
> Kevin Neilson <kevin_neilson@removethiscomcast.net> writes:
> 
>> thutt wrote:
>>> Hello everyone,
>>> I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
>>> because it's so slow and cumbersome to use.  What I'd like to do is
>>> output a netlist and use another script to process that netlist into
>>> input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
>>> I have figured out how to get the Xilinx tools to output a netlist,
>>> but it appears they output a 'technology' version and not an 'RTL'
>>> version of the netlist.
>>> Is there any way to get the tools to output a netlist that is in the
>>> more useful (to me) 'RTL' format?
>>> My desire is to be able to write VHDL code, build it with my build
>>> process and check the RTL without ever having to enter Xilinx's IDE.
>>> I'd also like to be able to easily extract schematics for inclusion
>>> into the chronicle of my personal project at
>>> http://www.harp-project.com/, but the Xilnix tools make this
>>> incredibly difficult.
>>> Thanks for any info,
>>> thutt
>>>
>> I think the RTL schematic is in a proprietary format.  I don't know if
>> it's possible to view it in another tool.  If you want a better viewer
>> for the technology schematic, you can import the NGC into PlanAhead,
>> which now comes with ISE.  If you want a better RTL viewer, you
>> probably have to resynthesize with a different synthesizer and view
>> the schematic in that tool.  -Kevin
> 
> I don't understand how the RTL can be in a proprietary format, if I'm
> reading the technology schematic correctly.  As far as I can tell,
> each LUT in the technology schematic represents some level of
> 'complex' logic which can be viewed in RTL form by double clicking on
> the LUT in the technology schematic viewer.
> 
> Each LUT also has an associated initialization value, a 16-bit
> hexadecimal number; I assume that the initialization value is the key
> which turns the lock and causes the LUT to implement a certain
> functionality.
> 
> If that's the case, has anyone spent the time to figure out the
> mappings of initialization codes to LUT implementations?  Or, does
> Xilinx publish this information?  (I seem to recall a post in either
> this newsgroup or comp.lang.vhdl which described how this was derived,
> but I don't recall if it went into any specificity with regards to
> Xilinx initialization values).
> 
> If there were a lookup table of initialization values to the standard
> 'and / or / xor'-type logic that each represents, then it would be
> quite possible to write a script to make an external RTL viewer based
> on the technology netlist output by the Xilinx tools.
> 
> Anyone game for a little sleuthing to determine all the LUT init
> codes?
> 
> thutt
The problem with turning a technology schematic into an RTL schematic is 
akin to turning object code into C.  Sure, you can determine that a LUT 
with a INIT code of FFFE is an inverter.  But it's hard determine that a 
collection of 80 LUTs is an adder, which you want to represent on an RTL 
schematic with a "+" sign, not as a bunch of XORs.
-Kevin

Brian Drummond wrote:
> On 20 Sep 2008 09:48:58 -0700, thutt <thutt151@comcast.net> wrote:
> 
>> Hello everyone,
>>
>> I'm tired of using the Xilinx ISE to look at RTL schematics, mainly
>> because it's so slow and cumbersome to use.  What I'd like to do is
>> output a netlist and use another script to process that netlist into
>> input suitable for VCG (http://rw4.cs.uni-sb.de/~sander/html/gsvcg1.html).
>>
>> I have figured out how to get the Xilinx tools to output a netlist,
>> but it appears they output a 'technology' version and not an 'RTL'
>> version of the netlist.
> 
>> Is there any way to get the tools to output a netlist that is in the
>> more useful (to me) 'RTL' format?
> 
> Have you looked at the post-synthesis simulation model (in VHDL)?
> 
> - Brian
The post-synthesis simulation model, if viewed in a different tool, 
would be about identical to a technology schematic, because all large 
structures have been resolved into primitives.
-Kevin