Altera and DDR3

I've been told that Altera has patented I/O technology that makes DDR3
interfacing "better" (in quotes because that could mean anything).  I
received this answer when I asked about DDR3 support since we are
considering migrating from Xilinx to Altera.  The answer was that
Altera, due to this technology, is able to support DDR3 at 533MHz
clock rate while Xilinx seems to be tentative about 400MHz support.

What's the real story?

-Martin

m wrote:
> I've been told that Altera has patented I/O technology that makes DDR3
> interfacing "better" (in quotes because that could mean anything).  I
> received this answer when I asked about DDR3 support since we are
> considering migrating from Xilinx to Altera.  The answer was that
> Altera, due to this technology, is able to support DDR3 at 533MHz
> clock rate while Xilinx seems to be tentative about 400MHz support.
> 
> What's the real story?

I don't know, but I can guess something. No idea, if this is even close,
haven't looked at Altera parts for awhile...

In DDR2 (and I suppose it's the same for DDR3) the memory chips have
On-Die-Termination (ODT), that can be turned on and off through a
dedicated IO. The idea is that you only turn it on when you send data
towards the memory chip, so there's a termination at the end of the
transmission line. The rest of the time the termination is turned off to
conserve power and avoid detrimental effects if you want to transmit the
OTHER way (i.e. from the memory chip to the controller, e.g. the FPGA).

Now, ideally this should be possible on BOTH sides, that is the
termination should be switchable on the side of the controller as well.
I know that in Xilinx devices this is not possible. DCIs are either
turned on or off permanently, it's "hardwired" in the bitstream. That
usually means that you burn tons of power and signal integrity is not
the optimum it could be.

Maybe recent Altera devices have the ability to turn off IO terminations
during operation? That would explain it and could be helpful.

That's my guess, for what it's worth. :)

cu,
Sean

On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote:
> I've been told that Altera has patented I/O technology that makes DDR3
> interfacing "better" (in quotes because that could mean anything). =A0I
> received this answer when I asked about DDR3 support since we are
> considering migrating from Xilinx to Altera. =A0The answer was that
> Altera, due to this technology, is able to support DDR3 at 533MHz
> clock rate while Xilinx seems to be tentative about 400MHz support.
>
> What's the real story?
>
> -Martin

AFIK the big difference is that Altera have technology that allows
continual monitoring and adjustment of the IO delays. This means that
the uncertainties are reduced and they can run at higher frequencies.
Also, Altera have IP solutions for DIMMs, but I believe that Xilinx
will only support components at the moment. Interfacing to DIMMs is
much harder than a single component because the address and control
signals are routed in a "fly-by" topology meaning that reads and
writes need to be levelled.

HTH
Rob

On Sep 22, 10:23=A0am, Rob <BertyBoos...@googlemail.com> wrote:
> On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote:
>
> > I've been told that Altera has patented I/O technology that makes DDR3
> > interfacing "better" (in quotes because that could mean anything). =A0I
> > received this answer when I asked about DDR3 support since we are
> > considering migrating from Xilinx to Altera. =A0The answer was that
> > Altera, due to this technology, is able to support DDR3 at 533MHz
> > clock rate while Xilinx seems to be tentative about 400MHz support.
>
> > What's the real story?
>
> > -Martin


The two features that are new in Stratix III and Stratix IV devices to
make DDR3 interfacing easier/possible are:

1.  Read and write leveling circuitry.  As Rob said, this makes
interfacing to DDR3 DIMMs feasible.  It compensates for the fact that
the clocks on DDR3 dimms are routed in a "fly-by" topology rather than
as a tree.  This means there is a different clock delay to each memory
chip (which is a pain), but it helps signal integrity because you can
terminate this line properly (while you can't terminate a tree well).
To deal with the fact that each memory chip has a different clock
delay, you need "read leveling" circuitry in your I/Os to get all the
data from various DQS groups (which came from different memory chips)
lined up on a single clock edge so you can send it in to your design.
You also need "write leveling" circuitry to skew the write data from
the FPGA to meet the tDQSS spec of the memory chip.

2.  Dynamic on-chip termination.  For the best signal integrity, you
really want to have your FPGA I/O act as a resistor when it is reading
from the memory chip.  But you don't want a parallel resistor when the
FPGA is writing to the memory chip or sending commands; that just
wastes power, and hurts signal integrity.  Dynamic on-chip termination
solves this -- it make the I/O behave like a resistor to Vtt during a
read, and makes it an impedence matched driver when it is writing to
the memory.

See http://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techniq=
ues-in-DDR3-SDRAM.pdf
for more detail.

Hope this helps.

Vaughn Betz
Altera
[v b e t z (at) altera.com]

On Sep 23, 2:03=A0am, vaughnb...@gmail.com wrote:
> On Sep 22, 10:23=A0am, Rob <BertyBoos...@googlemail.com> wrote:
>
> > On Sep 20, 7:43=A0pm, m <martin.use...@gmail.com> wrote:
>
> > > I've been told that Altera has patented I/O technology that makes DDR=
3
> > > interfacing "better" (in quotes because that could mean anything). =
=A0I
> > > received this answer when I asked about DDR3 support since we are
> > > considering migrating from Xilinx to Altera. =A0The answer was that
> > > Altera, due to this technology, is able to support DDR3 at 533MHz
> > > clock rate while Xilinx seems to be tentative about 400MHz support.
>
> > > What's the real story?
>
> > > -Martin
>
> The two features that are new in Stratix III and Stratix IV devices to
> make DDR3 interfacing easier/possible are:
>
> 1. =A0Read and write leveling circuitry. =A0As Rob said, this makes
> interfacing to DDR3 DIMMs feasible. =A0It compensates for the fact that
> the clocks on DDR3 dimms are routed in a "fly-by" topology rather than
> as a tree. =A0This means there is a different clock delay to each memory
> chip (which is a pain), but it helps signal integrity because you can
> terminate this line properly (while you can't terminate a tree well).
> To deal with the fact that each memory chip has a different clock
> delay, you need "read leveling" circuitry in your I/Os to get all the
> data from various DQS groups (which came from different memory chips)
> lined up on a single clock edge so you can send it in to your design.
> You also need "write leveling" circuitry to skew the write data from
> the FPGA to meet the tDQSS spec of the memory chip.
>
> 2. =A0Dynamic on-chip termination. =A0For the best signal integrity, you
> really want to have your FPGA I/O act as a resistor when it is reading
> from the memory chip. =A0But you don't want a parallel resistor when the
> FPGA is writing to the memory chip or sending commands; that just
> wastes power, and hurts signal integrity. =A0Dynamic on-chip termination
> solves this -- it make the I/O behave like a resistor to Vtt during a
> read, and makes it an impedence matched driver when it is writing to
> the memory.
>
> Seehttp://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techn.=
..
> for more detail.
>
> Hope this helps.
>
> Vaughn Betz
> Altera
> [v b e t z (at) altera.com]

OK, well I was half right ;-)

Interestingly, Xilinx do appear to have some kind of implementation
for dynamic termination. SSTL18_II_T_DCI appeared in the user guide
recently and removes the parallel termination when tri-stated. I've
tried to use this, but unfortunately it couldn't be mixed with
DIFF_SSTL18_II_DCI nets I had on the same bank.

> Seehttp://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techn...
> for more detail.

OK, that makes sense.  Do the Arria parts have this capability as
well?

Which parts can support a 533MHz DDR3 clock right now?


-Martin

On Sep 23, 8:28=A0am, m <martin.use...@gmail.com> wrote:
> > Seehttp://www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Tech=
n...
> > for more detail.
>
> OK, that makes sense. =A0Do the Arria parts have this capability as
> well?

Nope, they don't have dynamic OCT or read/write leveling circuitry.

> Which parts can support a 533MHz DDR3 clock right now?


The fastest (-2) Stratix III speed-grade supports 533 MHz DDR3, but as
the datasheet says (see http://www.altera.com/literature/hb/stx3/stx3_siii5=
1008.pdf)
fine-tuning of the DDR3 IP core for 533 MHz operation is not complete,
so you should not go into production at 533 MHz DDR3 with the current
(8.0) version of Quartus.

Vaughn
Altera
[v b e t z (at) altera.com]