Forums

Problem with mpmc(4.02.a) simulation -- DDR never initializes

Started by rao September 29, 2008
Hi,

  I am trying to simulate a EDK system based on microblaze.
  I have 10 slaves and one of the slave is a mpmc(4.02.a) and has
  microblaze i/d cache connections on 2 ports and a external DDR
interface
  on third port.
  I have a simple program that performs read and write to register
  bits in each of the slaves. All the slaves on the bus are responding
  except mpmc. When I tried to probe I found out that the
"MPMC_InitDone"
  stayed low for a long time. Seems like ddr never initializes there
by
  the slave interface(SPLB2) on mpmc doesn't respond to read/write to
  ddr.

  EDK Version : 10.1 SP2.

  Below is mpmc definition in my mhs file.

  -----------------------------------------------------
  BEGIN mpmc
  PARAMETER INSTANCE = mpmc_0
  PARAMETER HW_VER = 4.02.a
  PARAMETER C_FAMILY = virtex5
  PARAMETER C_PIM0_BASETYPE = 1
  PARAMETER C_PIM1_BASETYPE = 1
  PARAMETER C_PIM2_BASETYPE = 2
  PARAMETER C_NUM_PORTS = 3
  PARAMETER C_MPMC_BASEADDR = 0xEC000000
  PARAMETER C_MPMC_HIGHADDR = 0xEFFFFFFF
  # ### Memory and Memory Part Parameters
  PARAMETER C_MEM_TYPE = DDR
  PARAMETER C_MEM_PARTNO = MT46V32M16-6
  PARAMETER C_MEM_PART_TDQSS = 1
  PARAMETER C_MEM_PART_TAL = 0
  PARAMETER C_MPMC_CLK0_PERIOD_PS = 11740
  PARAMETER C_MEM_CLK_WIDTH = 1
  PARAMETER C_MEM_CE_WIDTH = 1
  PARAMETER C_MEM_CS_N_WIDTH = 1
  PARAMETER C_MEM_DATA_WIDTH = 16
  PARAMETER C_MEM_BITS_DATA_PER_DQS = 8
  PARAMETER C_MEM_NUM_RANKS = 1
  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y1
  PARAMETER C_XCL0_WRITEXFER = 0
  PARAMETER C_SPLB2_NATIVE_DWIDTH = 32
  PARAMETER C_SKIP_SIM_INIT_DELAY = 1
  BUS_INTERFACE SPLB2 = mb_plb
  # ###
  PORT MPMC_Clk0 = sys_clk_s
  PORT MPMC_Clk90 = sys_clk90_s
  PORT MPMC_Clk_200MHz = cpu_ddr_idelay_clk
  PORT MPMC_Rst = sys_rst_s
  PORT SPLB2_Clk = sys_clk_s
  PORT SPLB2_Rst = sys_rst_s
  PORT MPMC_InitDone = ddr_init_done
 # ###
  PORT DDR_Clk = ddr_clk
  PORT DDR_Clk_n = ddr_clk_n
  PORT DDR_CE = ddr_cke
  PORT DDR_CS_n = ddr_cs_n
  PORT DDR_RAS_n = ddr_ras_n
  PORT DDR_CAS_n = ddr_cas_n
  PORT DDR_WE_n = ddr_we_n
  PORT DDR_BankAddr = ddr_ba
  PORT DDR_Addr = ddr_a
  PORT DDR_DQ = CPU_DDR_DQ
  PORT DDR_DM = ddr_dqm
  PORT DDR_DQS = CPU_DDR_DQS
  END
  --------------------------------------------------

  I have checked clocks and reset and they are fine.

  I appreciate if anyone can point me in right direction.

Thanks
Rao
On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <raonpc@gmail.com> wrote:

>Hi, > > I am trying to simulate a EDK system based on microblaze. > I have 10 slaves and one of the slave is a mpmc(4.02.a) and has > microblaze i/d cache connections on 2 ports and a external DDR >interface > on third port. > I have a simple program that performs read and write to register > bits in each of the slaves. All the slaves on the bus are responding > except mpmc. When I tried to probe I found out that the >"MPMC_InitDone" > stayed low for a long time.
What is "a long time" in this context? Remember that a full initialisation sequence for DDR memory is supposed to take slightly over 200 us. Which is quite a long time in a simulator. How long is your simulation? - Brian
On Sep 29, 4:22=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote: > >Hi, > > > =A0I am trying to simulate a EDK system based on microblaze. > > =A0I have 10 slaves and one of the slave is a mpmc(4.02.a) and has > > =A0microblaze i/d cache connections on 2 ports and a external DDR > >interface > > =A0on third port. > > =A0I have a simple program that performs read and write to register > > =A0bits in each of the slaves. All the slaves on the bus are responding > > =A0except mpmc. When I tried to probe I found out that the > >"MPMC_InitDone" > > =A0stayed low for a long time. > > What is "a long time" in this context? > > Remember that a full initialisation sequence for DDR memory is supposed > to take slightly over 200 us. Which is quite a long time in a simulator. > > How long is your simulation? > > - Brian
Hi Brian, Thanks for the tip. I caught this init_done at almost 580us. I was expecting very short init_done as I was setting "PARAMETER C_SKIP_SIM_INIT_DELAY =3D 1". You saved lot of time as I was thinking of ripping the design to have only mpmc for the debug. Thanks again Rao
On Mon, 29 Sep 2008 17:14:57 -0700 (PDT), rao <raonpc@gmail.com> wrote:

>On Sep 29, 4:22&#2013266080;pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote: >> >Hi, >> >> > &#2013266080; When I tried to probe I found out that the >> >"MPMC_InitDone" >> > &#2013266080;stayed low for a long time. >> >> What is "a long time" in this context? >> >> Remember that a full initialisation sequence for DDR memory is supposed >> to take slightly over 200 us. Which is quite a long time in a simulator. >> >> How long is your simulation? >> >> - Brian > >Hi Brian, > Thanks for the tip. I caught this init_done at almost 580us. > > I was expecting very short init_done as I was setting > "PARAMETER C_SKIP_SIM_INIT_DELAY = 1". > > You saved lot of time as I was thinking of ripping the design > to have only mpmc for the debug.
To be honest, 580 us would surprise me too, but I don't know the internal details of MPMC. If it needs some intervention from the host (PPC or Microblaze), that would explain it. I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY. Does initialisation take another 200 us without it? Anyway I am glad the simulation is basically working. - Brian
On Sep 30, 4:53=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 29 Sep 2008 17:14:57 -0700 (PDT), rao <rao...@gmail.com> wrote: > >On Sep 29, 4:22=A0pm, Brian Drummond <brian_drumm...@btconnect.com> > >wrote: > >> On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote=
:
> >> >Hi, > > >> > =A0 When I tried to probe I found out that the > >> >"MPMC_InitDone" > >> > =A0stayed low for a long time. > > >> What is "a long time" in this context? > > >> Remember that a full initialisation sequence for DDR memory is suppose=
d
> >> to take slightly over 200 us. Which is quite a long time in a simulato=
r.
> > >> How long is your simulation? > > >> - Brian > > >Hi Brian, > > =A0Thanks for the tip. I caught this init_done at almost 580us. > > > =A0I was expecting very short init_done as I was setting > > =A0"PARAMETER C_SKIP_SIM_INIT_DELAY =3D 1". > > > You saved lot of time as I was thinking of ripping the design > > =A0to have only mpmc for the debug. > > To be honest, 580 us would surprise me too, but I don't know the > internal details of MPMC. If it needs some intervention from the host > (PPC or Microblaze), that would explain it. > > I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY. > Does initialisation take another 200 us without it? > > Anyway I am glad the simulation is basically working. > > - Brian
I have seen similar timing with MIG 2.2 and DDR 2 memory attached to a Virtex 5. It seems that the controller does a lot of calibration cycles to the DRAM. I don't think that the 200 uS startup delay was included as I also set the appropriate bit to skip it during simulation. If you use the Micron models for simulation you can see all of the cycles being performed in the simulation transcript. These tend to be reads and writes (mostly reads) and the data flips between all zeroes and all ones (looks like calibration). You will also see that the first access to the Mode register of the DRAMs comes well before 200 uS indicating that the warm-up delay was indeed skipped. I don't know how to work around this without either finding a smarter DDR memory core or getting a better simulator (or license) to allow reasonable simulation run times. Regards, Gabor
On Wed, 1 Oct 2008 08:14:38 -0700 (PDT), Gabor <gabor@alacron.com>
wrote:

>On Sep 30, 4:53&#2013266080;am, Brian Drummond <brian_drumm...@btconnect.com> >wrote:
>> To be honest, 580 us would surprise me too, but I don't know the >> internal details of MPMC. If it needs some intervention from the host >> (PPC or Microblaze), that would explain it. >> >> I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY. >> Does initialisation take another 200 us without it? >> >> Anyway I am glad the simulation is basically working. >> >> - Brian > >I have seen similar timing with MIG 2.2 and DDR 2 memory attached to a >Virtex 5. > >It seems that the controller does a lot of calibration cycles to the >DRAM. I don't >think that the 200 uS startup delay was included as I also set the >appropriate >bit to skip it during simulation.
Good answer to both questions; I think we have an explanation for the long startup time, and verified that it cannot easily be further reduced. - Brian