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How to synthesize a delay of around 10 ns in FPGA?

Started by Pratap ●October 8, 2008
Summary A user seeks a method to implement a fixed 10 ns delay in a Xilinx Virtex-2 Pro FPGA, noting that simple inverter chains are removed by logic optimization.

A user seeks a method to implement a fixed 10 ns delay in a Xilinx Virtex-2 Pro FPGA, noting that simple inverter chains are removed by logic optimization. The discussion explores why combinatorial delays are unreliable due to temperature and voltage fluctuations and suggests hardware-specific alternatives for better stability.

The consensus emphasizes moving away from asynchronous inverter chains in favor of clock-based solutions, Digital Clock Managers (DCM), or the IDELAY primitive available in newer Xilinx families.

  • Logic optimizers automatically remove redundant inverter chains unless specifically prevented by LUT instantiation or XOR logic tricks.
  • Combinatorial delays are highly unstable as they vary significantly with temperature, voltage, and routing overhead.
  • Using a Digital Clock Manager (DCM) or a phase-shifted clock is the recommended way to achieve precise, stable timing offsets.
  • For newer Xilinx families like Virtex-4, the IDELAY primitive provides a 'servo-stabilized' hardware delay that is much more reliable than logic-based delays.
  • Routing delays in FPGAs often exceed the logic delay of the gates themselves, making manual placement necessary for custom delay lines.
FPGA DesignXilinx VirtexHardware TimingLogic Optimization
Hi,
I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
I put around 200 inverters in series and get the desired delay. So I
did port map the BASIC cell "INV" according to the XST settings.
But when i place and route I guess the optimizer removes all the
intermediate buffers and I get very less delay when I do a post route
simulation.
How can I get rid of this problem?
Thanks in advance.
-Pratap
Reply by ●October 8, 20082008-10-08
On 8 okt, 16:35, Pratap <pratap.i...@gmail.com> wrote:

> Hi,
> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> I put around 200 inverters in series and get the desired delay. So I
> did port map the BASIC cell "INV" according to the XST settings.
> But when i place and route I guess the optimizer removes all the
> intermediate buffers and I get very less delay when I do a post route
> simulation.
> How can I get rid of this problem?
> Thanks in advance.
> -Pratap


If you have a clock signal of 100MHz, then just delay with one clock
tick...
Reply by Gabor ●October 8, 20082008-10-08
On Oct 8, 10:35=A0am, Pratap <pratap.i...@gmail.com> wrote:

> Hi,
> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> I put around 200 inverters in series and get the desired delay. So I
> did port map the BASIC cell "INV" according to the XST settings.
> But when i place and route I guess the optimizer removes all the
> intermediate buffers and I get very less delay when I do a post route
> simulation.
> How can I get rid of this problem?
> Thanks in advance.
> -Pratap


First of all, 200 inverters may have about 10nS delay, but the routing
to
connect them will have many times this much.

Second, any number of inverters greater than 1 will be optimised.  To
keep your logic, it's better to instantiate LUT components (assuming
you don't decide to use a clock instead).  Check out the libraries
guide
for available LUT's in your logic family.  You can also use carry
chain
elements for finer delay resolution (because of dedicated routing).

Regards,
Gabor
Reply by Symon ●October 8, 20082008-10-08
<lbraeckm@gmail.com> wrote in message 
news:84d1168c-6ccc-4847-b36a-390fbd9dc425@v39g2000pro.googlegroups.com...

> On 8 okt, 16:35, Pratap <pratap.i...@gmail.com> wrote:
>> Hi,
>> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
>> I put around 200 inverters in series and get the desired delay.
>> -Pratap
>
> If you have a clock signal of 100MHz, then just delay with one clock
> tick...


I get the feeling that isn't what the OP wants. Your suggestion will give a 
delay of between the FF's clock to out and 10ns plus clock to out, for an 
asynchronous input.
Cheers, Syms.
Reply by Peter Alfke ●October 8, 20082008-10-08
On Oct 8, 7:35=A0am, Pratap <pratap.i...@gmail.com> wrote:

> Hi,
> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> I put around 200 inverters in series and get the desired delay. So I
> did port map the BASIC cell "INV" according to the XST settings.
> But when i place and route I guess the optimizer removes all the
> intermediate buffers and I get very less delay when I do a post route
> simulation.
> How can I get rid of this problem?
> Thanks in advance.
> -Pratap


Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
delay, but that delay is stable over temperature, voltage, and
processing, because it is referenced to a 200 MHz clock (I call that
servo-stabilized).
Peter Alfke, Xilinx
Reply by KJ ●October 8, 20082008-10-08
On Oct 8, 10:35=A0am, Pratap <pratap.i...@gmail.com> wrote:

> Hi,
> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> I put around 200 inverters in series and get the desired delay. So I
> did port map the BASIC cell "INV" according to the XST settings.
> But when i place and route I guess the optimizer removes all the
> intermediate buffers and I get very less delay when I do a post route
> simulation.


Logically a string of 2n inverters can be replaced with a wire.
Logically a string of 2n+1 inverters can be replaced with a wire and a
change to the contents of the LUT(s) that use that inverted signal.

That's exactly what logic optimizers do.


> How can I get rid of this problem?
> Thanks in advance.


1. There really is no good and reliable method for generating fixed
time delays in an FPGA without a free running clock.
2. 10 ns +/- ??.  In other words, what sort of tolerance on the
nominal 10 ns is acceptable?  The tighter the tolerance the harder it
becomes.
3. Most times when people think they need a delay line, they really
don't because there are better and more robust ways to implement the
design that do not require a delay line.  You might want to describe
what you're doing and why you think you need the delay line.  That
should generate responses on alternative design approaches.

Kevin Jennings
Reply by Thomas Heller ●October 8, 20082008-10-08
Peter Alfke schrieb:

[Ah, back again?]


> On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
>> Hi,
>> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
>> I put around 200 inverters in series and get the desired delay. So I
>> did port map the BASIC cell "INV" according to the XST settings.
>> But when i place and route I guess the optimizer removes all the
>> intermediate buffers and I get very less delay when I do a post route
>> simulation.
>> How can I get rid of this problem?
>> Thanks in advance.
>> -Pratap
> 
> Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> delay, but that delay is stable over temperature, voltage, and
> processing, because it is referenced to a 200 MHz clock (I call that
> servo-stabilized).
> Peter Alfke, Xilinx


Which jitter does this give?

Thanks,
Thomas
Reply by Peter Alfke ●October 8, 20082008-10-08
On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:

> Peter Alfke schrieb:
>
> [Ah, back again?]
>
>
>
> > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> >> Hi,
> >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> >> I put around 200 inverters in series and get the desired delay. So I
> >> did port map the BASIC cell "INV" according to the XST settings.
> >> But when i place and route I guess the optimizer removes all the
> >> intermediate buffers and I get very less delay when I do a post route
> >> simulation.
> >> How can I get rid of this problem?
> >> Thanks in advance.
> >> -Pratap
>
> > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > delay, but that delay is stable over temperature, voltage, and
> > processing, because it is referenced to a 200 MHz clock (I call that
> > servo-stabilized).
> > Peter Alfke, Xilinx
>
> Which jitter does this give?
>
> Thanks,
> Thomas


Very little, since this is really a string of concatenated 75-ps delay
elements, held constant by a 200 MHz oscillator that controls the
delay stable through Vcc adjustments.
You can even modulate this delay by 10% up and down.
Teaching is addictive...
Peter A.
Reply by Selensky ●October 8, 20082008-10-08
On 8 out, 18:31, Peter Alfke <pe...@xilinx.com> wrote:

> On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
>
>
>
> > Peter Alfke schrieb:
>
> > [Ah, back again?]
>
> > > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> > >> Hi,
> > >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. =

So

> > >> I put around 200 inverters in series and get the desired delay. So I
> > >> did port map the BASIC cell "INV" according to the XST settings.
> > >> But when i place and route I guess the optimizer removes all the
> > >> intermediate buffers and I get very less delay when I do a post rout=

e

> > >> simulation.
> > >> How can I get rid of this problem?
> > >> Thanks in advance.
> > >> -Pratap
>
> > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > > delay, but that delay is stable over temperature, voltage, and
> > > processing, because it is referenced to a 200 MHz clock (I call that
> > > servo-stabilized).
> > > Peter Alfke, Xilinx
>
> > Which jitter does this give?
>
> > Thanks,
> > Thomas
>
> Very little, since this is really a string of concatenated 75-ps delay
> elements, held constant by a 200 MHz oscillator that controls the
> delay stable through Vcc adjustments.
> You can even modulate this delay by 10% up and down.
> Teaching is addictive...
> Peter A.


Hi Peter,

You said that Virtex-4 IDELAY element is stable over temperature,
voltage and processing. Is it stable over continuous years of
operation too?
In our project we are currently using IDELAY to adjust optimal
sampling points in LVDS buses between two Virtex-4 devices (-11 grade)
@ 700 Mbps.
We want to know if PCB's issues like capacitance and humidity
variations would be more critical than FPGA deviations along
continuous years of operation.

Thanks,
Selensky
Reply by Peter Alfke ●October 9, 20082008-10-09
On Oct 8, 4:01=A0pm, Selensky <selen...@gmail.com> wrote:

> On 8 out, 18:31, Peter Alfke <pe...@xilinx.com> wrote:
>
>
>
> > On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
>
> > > Peter Alfke schrieb:
>
> > > [Ah, back again?]
>
> > > > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> > > >> Hi,
> > > >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro=

. So

> > > >> I put around 200 inverters in series and get the desired delay. So=

 I

> > > >> did port map the BASIC cell "INV" according to the XST settings.
> > > >> But when i place and route I guess the optimizer removes all the
> > > >> intermediate buffers and I get very less delay when I do a post ro=

ute

> > > >> simulation.
> > > >> How can I get rid of this problem?
> > > >> Thanks in advance.
> > > >> -Pratap
>
> > > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > > > delay, but that delay is stable over temperature, voltage, and
> > > > processing, because it is referenced to a 200 MHz clock (I call tha=

t

> > > > servo-stabilized).
> > > > Peter Alfke, Xilinx
>
> > > Which jitter does this give?
>
> > > Thanks,
> > > Thomas
>
> > Very little, since this is really a string of concatenated 75-ps delay
> > elements, held constant by a 200 MHz oscillator that controls the
> > delay stable through Vcc adjustments.
> > You can even modulate this delay by 10% up and down.
> > Teaching is addictive...
> > Peter A.
>
> Hi Peter,
>
> You said that Virtex-4 IDELAY element is stable over temperature,
> voltage and processing. Is it stable over continuous years of
> operation too?
> In our project we are currently using IDELAY to adjust optimal
> sampling points in LVDS buses between two Virtex-4 devices (-11 grade)
> @ 700 Mbps.
> We want to know if PCB's issues like capacitance and humidity
> variations would be more critical than FPGA deviations along
> continuous years of operation.
>
> Thanks,
> Selensky


No variations.
It is a Phase-Locked-Loop, controlled by a user oscillator of approx
200 MHz, which makes sure that the total delay over 64 taps is exactly
one period of 200 MHz.
It assumes that delays of neighboring IDELAY blocks track, but that is
a sure thing in ICs. Capacitance and humidity have no impact on a
digital control circuit.
The world is full of frequency synthesizers that rely on far more
complex PLL circuits, apparently without problems.
Peter Alfke, from home.