How to synthesize a delay of around 10 ns in FPGA?

On Oct 8, 4:01=A0pm, Selensky <selen...@gmail.com> wrote:
> On 8 out, 18:31, Peter Alfke <pe...@xilinx.com> wrote:
>
>
>
> > On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
>
> > > Peter Alfke schrieb:
>
> > > [Ah, back again?]
>
> > > > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> > > >> Hi,
> > > >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro=
. So
> > > >> I put around 200 inverters in series and get the desired delay. So=
 I
> > > >> did port map the BASIC cell "INV" according to the XST settings.
> > > >> But when i place and route I guess the optimizer removes all the
> > > >> intermediate buffers and I get very less delay when I do a post ro=
ute
> > > >> simulation.
> > > >> How can I get rid of this problem?
> > > >> Thanks in advance.
> > > >> -Pratap
>
> > > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > > > delay, but that delay is stable over temperature, voltage, and
> > > > processing, because it is referenced to a 200 MHz clock (I call tha=
t
> > > > servo-stabilized).
> > > > Peter Alfke, Xilinx
>
> > > Which jitter does this give?
>
> > > Thanks,
> > > Thomas
>
> > Very little, since this is really a string of concatenated 75-ps delay
> > elements, held constant by a 200 MHz oscillator that controls the
> > delay stable through Vcc adjustments.
> > You can even modulate this delay by 10% up and down.
> > Teaching is addictive...
> > Peter A.
>
> Hi Peter,
>
> You said that Virtex-4 IDELAY element is stable over temperature,
> voltage and processing. Is it stable over continuous years of
> operation too?
> In our project we are currently using IDELAY to adjust optimal
> sampling points in LVDS buses between two Virtex-4 devices (-11 grade)
> @ 700 Mbps.
> We want to know if PCB's issues like capacitance and humidity
> variations would be more critical than FPGA deviations along
> continuous years of operation.
>
> Thanks,
> Selensky

Sorry, I misunderstood your question.
You are asking whether the pc-board delay may change too much over
time.
My gut feel is that humidity has very little impact on the propagation
time, which is affected by the square root of C, so its impact would
also be fairly benign.
Peter

Peter Alfke schrieb:
> On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
>> Hi,
>> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
>> I put around 200 inverters in series and get the desired delay. So I
>> did port map the BASIC cell "INV" according to the XST settings.
>> But when i place and route I guess the optimizer removes all the
>> intermediate buffers and I get very less delay when I do a post route
>> simulation.
>> How can I get rid of this problem?
>> Thanks in advance.
>> -Pratap
> 
> Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> delay, but that delay is stable over temperature, voltage, and
> processing, because it is referenced to a 200 MHz clock (I call that
> servo-stabilized).
> Peter Alfke, Xilinx

Is IDELAY available in any spartan devices?

Thanks,
Thomas

On Oct 10, 4:15=A0am, Thomas Heller <thel...@python.net> wrote:
> Peter Alfke schrieb:
>
>
>
> > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> >> Hi,
> >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> >> I put around 200 inverters in series and get the desired delay. So I
> >> did port map the BASIC cell "INV" according to the XST settings.
> >> But when i place and route I guess the optimizer removes all the
> >> intermediate buffers and I get very less delay when I do a post route
> >> simulation.
> >> How can I get rid of this problem?
> >> Thanks in advance.
> >> -Pratap
>
> > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > delay, but that delay is stable over temperature, voltage, and
> > processing, because it is referenced to a 200 MHz clock (I call that
> > servo-stabilized).
> > Peter Alfke, Xilinx
>
> Is IDELAY available in any spartan devices?
>
> Thanks,
> Thomas

Only Virtex-4 and newer Virtex families have the "servo-stabilized"
IDELAY that I mentioned. Whenever Spartan has an IDELAY feature, the
user must cope with (compensate for) the temperature and voltage
dependence. As they say: "You gets what you pays for..." Spartan does
everything possible to keep the chip area small, and thus the cost
low.
Peter Alfke

On 9 Okt., 01:01, Selensky <selen...@gmail.com> wrote:
> Hi Peter,
> You said that Virtex-4 IDELAY element is stable over temperature,
> voltage and processing. Is it stable over continuous years of
> operation too?

While the IDELAY element itself is stable, IO routing inside the FPGA
is not.
Have a look at the tables at the end of XAPP856. They show that the
clock
vs. data routing show a relative drift of 1 delay tap with temperature
and 6
delay taps with supply voltage.
The data is for Virtex-5.

Kolja Sulimma

On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:

> Hi,
> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So I
> put around 200 inverters in series and get the desired delay. So I did
> port map the BASIC cell "INV" according to the XST settings. But when i
> place and route I guess the optimizer removes all the intermediate
> buffers and I get very less delay when I do a post route simulation.
> How can I get rid of this problem?
> Thanks in advance.
> -Pratap

Do you need a delay or can you accomplish your task with a phase shifted 
clock? If you can use a phase shifted clock from the DCM that's a much 
better way of doing it because it's stable over temperature and process 
and because it won't change when the tools change.

If you must build a delay line from buffers you will have to directly 
place them because the routing delays are much more important then the LUT 
delays. Also you should use an XOR instead of an inverter. Tie one side of 
the XOR to a flop which presets to 1 on reset and then clocks a zero into 
the data input. This will be enough to fool XST and PAR into leaving the 
components alone.

On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com>
wrote:
> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
> > Hi,
> > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So =
I
> > put around 200 inverters in series and get the desired delay. So I did
> > port map the BASIC cell "INV" according to the XST settings. But when i
> > place and route I guess the optimizer removes all the intermediate
> > buffers and I get very less delay when I do a post route simulation.
> > How can I get rid of this problem?
> > Thanks in advance.
> > -Pratap
>
> Do you need a delay or can you accomplish your task with a phase shifted
> clock? If you can use a phase shifted clock from the DCM that's a much
> better way of doing it because it's stable over temperature and process
> and because it won't change when the tools change.
>
> If you must build a delay line from buffers you will have to directly
> place them because the routing delays are much more important then the LU=
T
> delays. Also you should use an XOR instead of an inverter. Tie one side o=
f
> the XOR to a flop which presets to 1 on reset and then clocks a zero into
> the data input. This will be enough to fool XST and PAR into leaving the
> components alone.

Hi,
Can you please send me some good material on DCM?
I actually require to generating delays around 0 ps by having a
passive
delay of around 1 period and then increasing and decreasing the input
frequency slightly.Can DCM help me in that case?

On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com>
wrote:
> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
> > Hi,
> > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So =
I
> > put around 200 inverters in series and get the desired delay. So I did
> > port map the BASIC cell "INV" according to the XST settings. But when i
> > place and route I guess the optimizer removes all the intermediate
> > buffers and I get very less delay when I do a post route simulation.
> > How can I get rid of this problem?
> > Thanks in advance.
> > -Pratap
>
> Do you need a delay or can you accomplish your task with a phase shifted
> clock? If you can use a phase shifted clock from the DCM that's a much
> better way of doing it because it's stable over temperature and process
> and because it won't change when the tools change.
>
> If you must build a delay line from buffers you will have to directly
> place them because the routing delays are much more important then the LU=
T
> delays. Also you should use an XOR instead of an inverter. Tie one side o=
f
> the XOR to a flop which presets to 1 on reset and then clocks a zero into
> the data input. This will be enough to fool XST and PAR into leaving the
> components alone.

On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com>
wrote:
> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
> > Hi,
> > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So =
I
> > put around 200 inverters in series and get the desired delay. So I did
> > port map the BASIC cell "INV" according to the XST settings. But when i
> > place and route I guess the optimizer removes all the intermediate
> > buffers and I get very less delay when I do a post route simulation.
> > How can I get rid of this problem?
Hi,
Can you please send me some good material on DCM?
I actually require to generating delays around 0 ps by having a
passive
delay of around 1 period and then increasing and decreasing the input
frequency slightly.Can DCM help me in that case?
-pratap


> > Thanks in advance.
> > -Pratap
>
> Do you need a delay or can you accomplish your task with a phase shifted
> clock? If you can use a phase shifted clock from the DCM that's a much
> better way of doing it because it's stable over temperature and process
> and because it won't change when the tools change.
>
> If you must build a delay line from buffers you will have to directly
> place them because the routing delays are much more important then the LU=
T
> delays. Also you should use an XOR instead of an inverter. Tie one side o=
f
> the XOR to a flop which presets to 1 on reset and then clocks a zero into
> the data input. This will be enough to fool XST and PAR into leaving the
> components alone.

On Mon, 20 Oct 2008 15:30:49 -0700, Pratap wrote:

> On Oct 13, 6:59&nbsp;am, General Schvantzkopf <schvantzk...@yahoo.com> wrote:
>> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
>> > Hi,
>> > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro.
>> > So I put around 200 inverters in series and get the desired delay. So
>> > I did port map the BASIC cell "INV" according to the XST settings.
>> > But when i place and route I guess the optimizer removes all the
>> > intermediate buffers and I get very less delay when I do a post route
>> > simulation. How can I get rid of this problem?
> Hi,
> Can you please send me some good material on DCM? I actually require to
> generating delays around 0 ps by having a passive
> delay of around 1 period and then increasing and decreasing the input
> frequency slightly.Can DCM help me in that case? -pratap
> 
> 
>> > Thanks in advance.
>> > -Pratap
>>
>> Do you need a delay or can you accomplish your task with a phase
>> shifted clock? If you can use a phase shifted clock from the DCM that's
>> a much better way of doing it because it's stable over temperature and
>> process and because it won't change when the tools change.
>>
>> If you must build a delay line from buffers you will have to directly
>> place them because the routing delays are much more important then the
>> LUT delays. Also you should use an XOR instead of an inverter. Tie one
>> side of the XOR to a flop which presets to 1 on reset and then clocks a
>> zero into the data input. This will be enough to fool XST and PAR into
>> leaving the components alone.

Just read the Users Guide for the V2P

On Oct 20, 3:30=A0pm, Pratap <pratap.i...@gmail.com> wrote:
> On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com>
> wrote:> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote:
> > > Hi,
> > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. S=
o I
> > > put around 200 inverters in series and get the desired delay. So I di=
d
> > > port map the BASIC cell "INV" according to the XST settings. But when=
 i
> > > place and route I guess the optimizer removes all the intermediate
> > > buffers and I get very less delay when I do a post route simulation.
> > > How can I get rid of this problem?
>
> Hi,
> Can you please send me some good material on DCM?
> I actually require to generating delays around 0 ps by having a
> passive
> delay of around 1 period and then increasing and decreasing the input
> frequency slightly.Can DCM help me in that case?
> -pratap
>
> > > Thanks in advance.
> > > -Pratap
>
> > Do you need a delay or can you accomplish your task with a phase shifte=
d
> > clock? If you can use a phase shifted clock from the DCM that's a much
> > better way of doing it because it's stable over temperature and process
> > and because it won't change when the tools change.
>
> > If you must build a delay line from buffers you will have to directly
> > place them because the routing delays are much more important then the =
LUT
> > delays. Also you should use an XOR instead of an inverter. Tie one side=
 of
> > the XOR to a flop which presets to 1 on reset and then clocks a zero in=
to
> > the data input. This will be enough to fool XST and PAR into leaving th=
e
> > components alone.

The important question is: Who decides when to start your delay.
If you can wait until an oscillator has a rising edge, then there are
many high-quality solutions, especially when you know the delay value
well beforehand. With the help of frequency synthesis and PLLs, you
can generate a delay with very fine resolution, even below a
picosecond. (Of course you lose that accuracy as you propagate through
more logic.)
If, however, you need to be the master of starting the delay, then you
are much more constrained, and your best bet is what Virtex-4 and
later did by cascading analog delay elements, and servo-controlling
their composite delay. And the inherent accuracy will be not perfect,
with an error of a nanosecond, unless you get really creative.
Peter Alfke, lurking from home...